cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,gcc-sc8280xp.yaml (4208B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
      8
      9maintainers:
     10  - Bjorn Andersson <bjorn.andersson@linaro.org>
     11
     12description: |
     13  Qualcomm global clock control module which supports the clocks, resets and
     14  power domains on SC8280xp.
     15
     16  See also:
     17  - include/dt-bindings/clock/qcom,gcc-sc8280xp.h
     18
     19properties:
     20  compatible:
     21    const: qcom,gcc-sc8280xp
     22
     23  clocks:
     24    items:
     25      - description: XO reference clock
     26      - description: Sleep clock
     27      - description: UFS memory first RX symbol clock
     28      - description: UFS memory second RX symbol clock
     29      - description: UFS memory first TX symbol clock
     30      - description: UFS card first RX symbol clock
     31      - description: UFS card second RX symbol clock
     32      - description: UFS card first TX symbol clock
     33      - description: Primary USB SuperSpeed pipe clock
     34      - description: USB4 PHY pipegmux clock source
     35      - description: USB4 PHY DP gmux clock source
     36      - description: USB4 PHY sys piegmux clock source
     37      - description: USB4 PHY PCIe pipe clock
     38      - description: USB4 PHY router max pipe clock
     39      - description: Primary USB4 RX0 clock
     40      - description: Primary USB4 RX1 clock
     41      - description: Secondary USB SuperSpeed pipe clock
     42      - description: Second USB4 PHY pipegmux clock source
     43      - description: Second USB4 PHY DP gmux clock source
     44      - description: Second USB4 PHY sys pipegmux clock source
     45      - description: Second USB4 PHY PCIe pipe clock
     46      - description: Second USB4 PHY router max pipe clock
     47      - description: Secondary USB4 RX0 clock
     48      - description: Secondary USB4 RX1 clock
     49      - description: Multiport USB first SupserSpeed pipe clock
     50      - description: Multiport USB second SuperSpeed pipe clock
     51      - description: PCIe 2a pipe clock
     52      - description: PCIe 2b pipe clock
     53      - description: PCIe 3a pipe clock
     54      - description: PCIe 3b pipe clock
     55      - description: PCIe 4 pipe clock
     56      - description: First EMAC controller reference clock
     57      - description: Second EMAC controller reference clock
     58
     59  '#clock-cells':
     60    const: 1
     61
     62  '#reset-cells':
     63    const: 1
     64
     65  '#power-domain-cells':
     66    const: 1
     67
     68  reg:
     69    maxItems: 1
     70
     71  protected-clocks:
     72    maxItems: 389
     73
     74required:
     75  - compatible
     76  - clocks
     77  - reg
     78  - '#clock-cells'
     79  - '#reset-cells'
     80  - '#power-domain-cells'
     81
     82additionalProperties: false
     83
     84examples:
     85  - |
     86    #include <dt-bindings/clock/qcom,rpmh.h>
     87    clock-controller@100000 {
     88      compatible = "qcom,gcc-sc8280xp";
     89      reg = <0x00100000 0x1f0000>;
     90      clocks = <&rpmhcc RPMH_CXO_CLK>,
     91               <&sleep_clk>,
     92               <&ufs_phy_rx_symbol_0_clk>,
     93               <&ufs_phy_rx_symbol_1_clk>,
     94               <&ufs_phy_tx_symbol_0_clk>,
     95               <&ufs_card_rx_symbol_0_clk>,
     96               <&ufs_card_rx_symbol_1_clk>,
     97               <&ufs_card_tx_symbol_0_clk>,
     98               <&usb_0_ssphy>,
     99               <&gcc_usb4_phy_pipegmux_clk_src>,
    100               <&gcc_usb4_phy_dp_gmux_clk_src>,
    101               <&gcc_usb4_phy_sys_pipegmux_clk_src>,
    102               <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
    103               <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
    104               <&qusb4phy_gcc_usb4_rx0_clk>,
    105               <&qusb4phy_gcc_usb4_rx1_clk>,
    106               <&usb_1_ssphy>,
    107               <&gcc_usb4_1_phy_pipegmux_clk_src>,
    108               <&gcc_usb4_1_phy_dp_gmux_clk_src>,
    109               <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
    110               <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
    111               <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
    112               <&qusb4phy_1_gcc_usb4_rx0_clk>,
    113               <&qusb4phy_1_gcc_usb4_rx1_clk>,
    114               <&usb_2_ssphy>,
    115               <&usb_3_ssphy>,
    116               <&pcie2a_lane>,
    117               <&pcie2b_lane>,
    118               <&pcie3a_lane>,
    119               <&pcie3b_lane>,
    120               <&pcie4_lane>,
    121               <&rxc0_ref_clk>,
    122               <&rxc1_ref_clk>;
    123
    124      #clock-cells = <1>;
    125      #reset-cells = <1>;
    126      #power-domain-cells = <1>;
    127    };
    128...