cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,gcc-sdx65.yaml (1978B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Global Clock & Reset Controller Binding for SDX65
      8
      9maintainers:
     10  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
     11
     12description: |
     13  Qualcomm global clock control module which supports the clocks, resets and
     14  power domains on SDX65
     15
     16  See also:
     17  - dt-bindings/clock/qcom,gcc-sdx65.h
     18
     19properties:
     20  compatible:
     21    const: qcom,gcc-sdx65
     22
     23  reg:
     24    maxItems: 1
     25
     26  clocks:
     27    items:
     28      - description: Board XO source
     29      - description: Board active XO source
     30      - description: Sleep clock source
     31      - description: PCIE Pipe clock source
     32      - description: USB3 phy wrapper pipe clock source
     33      - description: PLL test clock source (Optional clock)
     34    minItems: 5
     35
     36  clock-names:
     37    items:
     38      - const: bi_tcxo
     39      - const: bi_tcxo_ao
     40      - const: sleep_clk
     41      - const: pcie_pipe_clk
     42      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
     43      - const: core_bi_pll_test_se # Optional clock
     44    minItems: 5
     45
     46  '#clock-cells':
     47    const: 1
     48
     49  '#reset-cells':
     50    const: 1
     51
     52  '#power-domain-cells':
     53    const: 1
     54
     55required:
     56  - compatible
     57  - reg
     58  - clocks
     59  - clock-names
     60  - '#clock-cells'
     61  - '#reset-cells'
     62  - '#power-domain-cells'
     63
     64additionalProperties: false
     65
     66examples:
     67  - |
     68    #include <dt-bindings/clock/qcom,rpmh.h>
     69    clock-controller@100000 {
     70      compatible = "qcom,gcc-sdx65";
     71      reg = <0x100000 0x1f7400>;
     72      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
     73               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
     74      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
     75                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
     76      #clock-cells = <1>;
     77      #reset-cells = <1>;
     78      #power-domain-cells = <1>;
     79    };
     80...