cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,gcc-sm6125.yaml (1486B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Global Clock & Reset Controller Binding for SM6125
      8
      9maintainers:
     10  - Konrad Dybcio <konrad.dybcio@somainline.org>
     11
     12description: |
     13  Qualcomm global clock control module which supports the clocks, resets and
     14  power domains on SM6125.
     15
     16  See also:
     17  - dt-bindings/clock/qcom,gcc-sm6125.h
     18
     19properties:
     20  compatible:
     21    const: qcom,gcc-sm6125
     22
     23  clocks:
     24    items:
     25      - description: Board XO source
     26      - description: Sleep clock source
     27
     28  clock-names:
     29    items:
     30      - const: bi_tcxo
     31      - const: sleep_clk
     32
     33  '#clock-cells':
     34    const: 1
     35
     36  '#reset-cells':
     37    const: 1
     38
     39  '#power-domain-cells':
     40    const: 1
     41
     42  reg:
     43    maxItems: 1
     44
     45  protected-clocks:
     46    description:
     47      Protected clock specifier list as per common clock binding.
     48
     49required:
     50  - compatible
     51  - clocks
     52  - clock-names
     53  - reg
     54  - '#clock-cells'
     55  - '#reset-cells'
     56  - '#power-domain-cells'
     57
     58additionalProperties: false
     59
     60examples:
     61  - |
     62    #include <dt-bindings/clock/qcom,rpmcc.h>
     63    clock-controller@1400000 {
     64        compatible = "qcom,gcc-sm6125";
     65        reg = <0x01400000 0x1f0000>;
     66        #clock-cells = <1>;
     67        #reset-cells = <1>;
     68        #power-domain-cells = <1>;
     69        clock-names = "bi_tcxo", "sleep_clk";
     70        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
     71    };
     72...