cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,gpucc-sdm660.yaml (1715B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
      8
      9maintainers:
     10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
     11
     12description: |
     13  Qualcomm graphics clock control module which supports the clocks, resets and
     14  power domains on SDM630 and SDM660.
     15
     16  See also dt-bindings/clock/qcom,gpucc-sdm660.h.
     17
     18properties:
     19  compatible:
     20    enum:
     21      - qcom,gpucc-sdm630
     22      - qcom,gpucc-sdm660
     23
     24  clocks:
     25    items:
     26      - description: Board XO source
     27      - description: GPLL0 main gpu branch
     28      - description: GPLL0 divider gpu branch
     29
     30  clock-names:
     31    items:
     32      - const: xo
     33      - const: gcc_gpu_gpll0_clk
     34      - const: gcc_gpu_gpll0_div_clk
     35
     36  '#clock-cells':
     37    const: 1
     38
     39  '#reset-cells':
     40    const: 1
     41
     42  '#power-domain-cells':
     43    const: 1
     44
     45  reg:
     46    maxItems: 1
     47
     48required:
     49  - compatible
     50  - reg
     51  - clocks
     52  - clock-names
     53  - '#clock-cells'
     54  - '#reset-cells'
     55  - '#power-domain-cells'
     56
     57additionalProperties: false
     58
     59examples:
     60  - |
     61    #include <dt-bindings/clock/qcom,gcc-sdm660.h>
     62    #include <dt-bindings/clock/qcom,rpmcc.h>
     63
     64    clock-controller@5065000 {
     65      compatible = "qcom,gpucc-sdm660";
     66      reg = <0x05065000 0x9038>;
     67      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
     68               <&gcc GCC_GPU_GPLL0_CLK>,
     69               <&gcc GCC_GPU_GPLL0_DIV_CLK>;
     70      clock-names = "xo", "gcc_gpu_gpll0_clk",
     71                    "gcc_gpu_gpll0_div_clk";
     72      #clock-cells = <1>;
     73      #power-domain-cells = <1>;
     74      #reset-cells = <1>;
     75    };
     76...