cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,mmcc.yaml (2332B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Multimedia Clock & Reset Controller Binding
      8
      9maintainers:
     10  - Jeffrey Hugo <quic_jhugo@quicinc.com>
     11  - Taniya Das <tdas@codeaurora.org>
     12
     13description: |
     14  Qualcomm multimedia clock control module which supports the clocks, resets and
     15  power domains.
     16
     17properties:
     18  compatible:
     19    enum:
     20      - qcom,mmcc-apq8064
     21      - qcom,mmcc-apq8084
     22      - qcom,mmcc-msm8226
     23      - qcom,mmcc-msm8660
     24      - qcom,mmcc-msm8960
     25      - qcom,mmcc-msm8974
     26      - qcom,mmcc-msm8992
     27      - qcom,mmcc-msm8994
     28      - qcom,mmcc-msm8996
     29      - qcom,mmcc-msm8998
     30      - qcom,mmcc-sdm630
     31      - qcom,mmcc-sdm660
     32
     33  clocks:
     34    items:
     35      - description: Board XO source
     36      - description: Board sleep source
     37      - description: Global PLL 0 clock
     38      - description: DSI phy instance 0 dsi clock
     39      - description: DSI phy instance 0 byte clock
     40      - description: DSI phy instance 1 dsi clock
     41      - description: DSI phy instance 1 byte clock
     42      - description: HDMI phy PLL clock
     43      - description: DisplayPort phy PLL vco clock
     44      - description: DisplayPort phy PLL link clock
     45
     46  clock-names:
     47    items:
     48      - const: xo
     49      - const: sleep
     50      - const: gpll0
     51      - const: dsi0dsi
     52      - const: dsi0byte
     53      - const: dsi1dsi
     54      - const: dsi1byte
     55      - const: hdmipll
     56      - const: dpvco
     57      - const: dplink
     58
     59  '#clock-cells':
     60    const: 1
     61
     62  '#reset-cells':
     63    const: 1
     64
     65  '#power-domain-cells':
     66    const: 1
     67
     68  reg:
     69    maxItems: 1
     70
     71  protected-clocks:
     72    description:
     73      Protected clock specifier list as per common clock binding
     74
     75  vdd-gfx-supply:
     76    description:
     77      Regulator supply for the GPU_GX GDSC
     78
     79required:
     80  - compatible
     81  - reg
     82  - '#clock-cells'
     83  - '#reset-cells'
     84  - '#power-domain-cells'
     85
     86additionalProperties: false
     87
     88if:
     89  properties:
     90    compatible:
     91      contains:
     92        const: qcom,mmcc-msm8998
     93
     94then:
     95  required:
     96    - clocks
     97    - clock-names
     98
     99examples:
    100  # Example for MMCC for MSM8960:
    101  - |
    102    clock-controller@4000000 {
    103      compatible = "qcom,mmcc-msm8960";
    104      reg = <0x4000000 0x1000>;
    105      #clock-cells = <1>;
    106      #reset-cells = <1>;
    107      #power-domain-cells = <1>;
    108    };
    109...