renesas,cpg-clocks.yaml (5600B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas Clock Pulse Generator (CPG) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12description: 13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It 14 includes PLLs, and fixed and variable ratio dividers. 15 16 The CPG may also provide a Clock Domain for SoC devices, in combination with 17 the CPG Module Stop (MSTP) Clocks. 18 19properties: 20 compatible: 21 oneOf: 22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6 23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1 24 - const: renesas,r8a7778-cpg-clocks # R-Car M1 25 - const: renesas,r8a7779-cpg-clocks # R-Car H1 26 - items: 27 - enum: 28 - renesas,r7s72100-cpg-clocks # RZ/A1H 29 - const: renesas,rz-cpg-clocks # RZ/A1 30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5 31 32 reg: 33 maxItems: 1 34 35 clocks: true 36 37 '#clock-cells': 38 const: 1 39 40 clock-output-names: true 41 42 renesas,mode: 43 description: Board-specific settings of the MD_CK* bits on R-Mobile A1 44 $ref: /schemas/types.yaml#/definitions/uint32 45 minimum: 0 46 maximum: 7 47 48 '#power-domain-cells': 49 const: 0 50 51required: 52 - compatible 53 - reg 54 - clocks 55 - '#clock-cells' 56 - clock-output-names 57 58allOf: 59 - if: 60 properties: 61 compatible: 62 contains: 63 const: renesas,r8a73a4-cpg-clocks 64 then: 65 properties: 66 clocks: 67 items: 68 - description: extal1 69 - description: extal2 70 71 clock-output-names: 72 items: 73 - const: main 74 - const: pll0 75 - const: pll1 76 - const: pll2 77 - const: pll2s 78 - const: pll2h 79 - const: z 80 - const: z2 81 - const: i 82 - const: m3 83 - const: b 84 - const: m1 85 - const: m2 86 - const: zx 87 - const: zs 88 - const: hp 89 90 - if: 91 properties: 92 compatible: 93 contains: 94 const: renesas,r8a7740-cpg-clocks 95 then: 96 properties: 97 clocks: 98 items: 99 - description: extal1 100 - description: extal2 101 - description: extalr 102 103 clock-output-names: 104 items: 105 - const: system 106 - const: pllc0 107 - const: pllc1 108 - const: pllc2 109 - const: r 110 - const: usb24s 111 - const: i 112 - const: zg 113 - const: b 114 - const: m1 115 - const: hp 116 - const: hpp 117 - const: usbp 118 - const: s 119 - const: zb 120 - const: m3 121 - const: cp 122 123 required: 124 - renesas,mode 125 126 - if: 127 properties: 128 compatible: 129 contains: 130 const: renesas,r8a7778-cpg-clocks 131 then: 132 properties: 133 clocks: 134 maxItems: 1 135 136 clock-output-names: 137 items: 138 - const: plla 139 - const: pllb 140 - const: b 141 - const: out 142 - const: p 143 - const: s 144 - const: s1 145 146 - if: 147 properties: 148 compatible: 149 contains: 150 const: renesas,r8a7779-cpg-clocks 151 then: 152 properties: 153 clocks: 154 maxItems: 1 155 156 clock-output-names: 157 items: 158 - const: plla 159 - const: z 160 - const: zs 161 - const: s 162 - const: s1 163 - const: p 164 - const: b 165 - const: out 166 167 - if: 168 properties: 169 compatible: 170 contains: 171 const: renesas,r7s72100-cpg-clocks 172 then: 173 properties: 174 clocks: 175 items: 176 - description: extal1 177 - description: usb_x1 178 179 clock-output-names: 180 items: 181 - const: pll 182 - const: i 183 - const: g 184 185 - if: 186 properties: 187 compatible: 188 contains: 189 const: renesas,sh73a0-cpg-clocks 190 then: 191 properties: 192 clocks: 193 items: 194 - description: extal1 195 - description: extal2 196 197 clock-output-names: 198 items: 199 - const: main 200 - const: pll0 201 - const: pll1 202 - const: pll2 203 - const: pll3 204 - const: dsi0phy 205 - const: dsi1phy 206 - const: zg 207 - const: m3 208 - const: b 209 - const: m1 210 - const: m2 211 - const: z 212 - const: zx 213 - const: hp 214 215 - if: 216 properties: 217 compatible: 218 contains: 219 enum: 220 - renesas,r8a7778-cpg-clocks 221 - renesas,r8a7779-cpg-clocks 222 - renesas,rz-cpg-clocks 223 then: 224 required: 225 - '#power-domain-cells' 226 227additionalProperties: false 228 229examples: 230 - | 231 #include <dt-bindings/clock/r8a7740-clock.h> 232 cpg_clocks: cpg_clocks@e6150000 { 233 compatible = "renesas,r8a7740-cpg-clocks"; 234 reg = <0xe6150000 0x10000>; 235 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; 236 #clock-cells = <1>; 237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", 238 "usb24s", "i", "zg", "b", "m1", "hp", "hpp", 239 "usbp", "s", "zb", "m3", "cp"; 240 renesas,mode = <0x05>; 241 };