cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

renesas,r9a06g032-sysctrl.yaml (1614B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas RZ/N1D (R9A06G032) System Controller
      8
      9maintainers:
     10  - Gareth Williams <gareth.williams.jx@renesas.com>
     11  - Geert Uytterhoeven <geert+renesas@glider.be>
     12
     13properties:
     14  compatible:
     15    const: renesas,r9a06g032-sysctrl
     16
     17  reg:
     18    maxItems: 1
     19
     20  clocks:
     21    minItems: 1
     22    items:
     23      - description: External 40 MHz crystal
     24      - description: Optional external 32.768 kHz crystal
     25      - description: Optional external JTAG input
     26      - description: Optional external RGMII_REFCLK
     27
     28  clock-names:
     29    minItems: 1
     30    items:
     31      - const: mclk
     32      - const: rtc
     33      - const: jtag
     34      - const: rgmii_ref_ext
     35
     36  '#clock-cells':
     37    const: 1
     38
     39  '#power-domain-cells':
     40    const: 0
     41
     42  '#address-cells':
     43    const: 1
     44
     45  '#size-cells':
     46    const: 1
     47
     48patternProperties:
     49  "^dma-router@[a-f0-9]+$":
     50    type: object
     51    $ref: "../dma/renesas,rzn1-dmamux.yaml#"
     52
     53required:
     54  - compatible
     55  - reg
     56  - clocks
     57  - clock-names
     58  - '#clock-cells'
     59  - '#power-domain-cells'
     60
     61additionalProperties: false
     62
     63examples:
     64  - |
     65    sysctrl: system-controller@4000c000 {
     66            compatible = "renesas,r9a06g032-sysctrl";
     67            reg = <0x4000c000 0x1000>;
     68            clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
     69                     <&ext_rgmii_ref>;
     70            clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
     71            #clock-cells = <1>;
     72            #power-domain-cells = <0>;
     73    };