cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,rzg2l-cpg.yaml (2846B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
      8
      9maintainers:
     10  - Geert Uytterhoeven <geert+renesas@glider.be>
     11
     12description: |
     13  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
     14  Standby Mode share the same register block. On RZ/V2M, the functionality is
     15  similar, but does not have Clock Monitor Registers.
     16
     17  They provide the following functionalities:
     18    - The CPG block generates various core clocks,
     19    - The Module Standby Mode block provides two functions:
     20        1. Module Standby, providing a Clock Domain to control the clock supply
     21           to individual SoC devices,
     22        2. Reset Control, to perform a software reset of individual SoC devices.
     23
     24properties:
     25  compatible:
     26    enum:
     27      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
     28      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
     29      - renesas,r9a07g054-cpg # RZ/V2L
     30      - renesas,r9a09g011-cpg # RZ/V2M
     31
     32  reg:
     33    maxItems: 1
     34
     35  clocks:
     36    maxItems: 1
     37
     38  clock-names:
     39    description:
     40      Clock source to CPG can be either from external clock input (EXCLK) or
     41      crystal oscillator (XIN/XOUT).
     42    const: extal
     43
     44  '#clock-cells':
     45    description: |
     46      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
     47        and a core clock reference, as defined in
     48        <dt-bindings/clock/r9a0*-cpg.h>
     49      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
     50        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
     51        <dt-bindings/clock/r9a09g011-cpg.h>.
     52    const: 2
     53
     54  '#power-domain-cells':
     55    description:
     56      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
     57      can be power-managed through Module Standby should refer to the CPG device
     58      node in their "power-domains" property, as documented by the generic PM
     59      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
     60    const: 0
     61
     62  '#reset-cells':
     63    description:
     64      The single reset specifier cell must be the module number, as defined in
     65      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
     66    const: 1
     67
     68required:
     69  - compatible
     70  - reg
     71  - clocks
     72  - clock-names
     73  - '#clock-cells'
     74  - '#power-domain-cells'
     75  - '#reset-cells'
     76
     77additionalProperties: false
     78
     79examples:
     80  - |
     81    cpg: clock-controller@11010000 {
     82            compatible = "renesas,r9a07g044-cpg";
     83            reg = <0x11010000 0x10000>;
     84            clocks = <&extal_clk>;
     85            clock-names = "extal";
     86            #clock-cells = <2>;
     87            #power-domain-cells = <0>;
     88            #reset-cells = <1>;
     89    };