rockchip,rk3128-cru.txt (1945B)
1* Rockchip RK3126/RK3128 Clock and Reset Unit 2 3The RK3126/RK3128 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru" 10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC. 11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC. 12- reg: physical base address of the controller and length of memory mapped 13 region. 14- #clock-cells: should be 1. 15- #reset-cells: should be 1. 16 17Optional Properties: 18 19- rockchip,grf: phandle to the syscon managing the "general register files" 20 If missing pll rates are not changeable, due to the missing pll lock status. 21 22Each clock is assigned an identifier and client nodes can use this identifier 23to specify the clock which they consume. All available clocks are defined as 24preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be 25used in device tree sources. Similar macros exist for the reset sources in 26these files. 27 28External clocks: 29 30There are several clocks that are generated outside the SoC. It is expected 31that they are defined using standard clock bindings with following 32clock-output-names: 33 - "xin24m" - crystal input - required, 34 - "ext_i2s" - external I2S clock - optional, 35 - "gmac_clkin" - external GMAC clock - optional 36 37Example: Clock controller node: 38 39 cru: cru@20000000 { 40 compatible = "rockchip,rk3128-cru"; 41 reg = <0x20000000 0x1000>; 42 rockchip,grf = <&grf>; 43 44 #clock-cells = <1>; 45 #reset-cells = <1>; 46 }; 47 48Example: UART controller node that consumes the clock generated by the clock 49 controller: 50 51 uart2: serial@20068000 { 52 compatible = "rockchip,serial"; 53 reg = <0x20068000 0x100>; 54 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 55 clock-frequency = <24000000>; 56 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 57 clock-names = "sclk_uart", "pclk_uart"; 58 };