cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip,rk3288-cru.yaml (2562B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip RK3288 Clock and Reset Unit (CRU)
      8
      9maintainers:
     10  - Elaine Zhang <zhangqing@rock-chips.com>
     11  - Heiko Stuebner <heiko@sntech.de>
     12
     13description: |
     14  The RK3288 clock controller generates and supplies clocks to various
     15  controllers within the SoC and also implements a reset controller for SoC
     16  peripherals.
     17
     18  A revision of this SoC is available: rk3288w. The clock tree is a bit
     19  different so another dt-compatible is available. Noticed that it is only
     20  setting the difference but there is no automatic revision detection. This
     21  should be performed by boot loaders.
     22
     23  Each clock is assigned an identifier and client nodes can use this identifier
     24  to specify the clock which they consume. All available clocks are defined as
     25  preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
     26  used in device tree sources. Similar macros exist for the reset sources in
     27  these files.
     28
     29  There are several clocks that are generated outside the SoC. It is expected
     30  that they are defined using standard clock bindings with following
     31  clock-output-names:
     32    - "xin24m"      - crystal input               - required,
     33    - "xin32k"      - rtc clock                   - optional,
     34    - "ext_i2s"     - external I2S clock          - optional,
     35    - "ext_hsadc"   - external HSADC clock        - optional,
     36    - "ext_edp_24m" - external display port clock - optional,
     37    - "ext_vip"     - external VIP clock          - optional,
     38    - "ext_isp"     - external ISP clock          - optional,
     39    - "ext_jtag"    - external JTAG clock         - optional
     40
     41properties:
     42  compatible:
     43    enum:
     44      - rockchip,rk3288-cru
     45      - rockchip,rk3288w-cru
     46
     47  reg:
     48    maxItems: 1
     49
     50  "#clock-cells":
     51    const: 1
     52
     53  "#reset-cells":
     54    const: 1
     55
     56  clocks:
     57    maxItems: 1
     58
     59  clock-names:
     60    const: xin24m
     61
     62  rockchip,grf:
     63    $ref: /schemas/types.yaml#/definitions/phandle
     64    description:
     65      Phandle to the syscon managing the "general register files" (GRF),
     66      if missing pll rates are not changeable, due to the missing pll
     67      lock status.
     68
     69required:
     70  - compatible
     71  - reg
     72  - "#clock-cells"
     73  - "#reset-cells"
     74
     75additionalProperties: false
     76
     77examples:
     78  - |
     79    cru: clock-controller@ff760000 {
     80      compatible = "rockchip,rk3288-cru";
     81      reg = <0xff760000 0x1000>;
     82      rockchip,grf = <&grf>;
     83      #clock-cells = <1>;
     84      #reset-cells = <1>;
     85    };