cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip,rk3368-cru.yaml (2401B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip RK3368 Clock and Reset Unit (CRU)
      8
      9maintainers:
     10  - Elaine Zhang <zhangqing@rock-chips.com>
     11  - Heiko Stuebner <heiko@sntech.de>
     12
     13description: |
     14  The RK3368 clock controller generates and supplies clocks to various
     15  controllers within the SoC and also implements a reset controller for SoC
     16  peripherals.
     17  Each clock is assigned an identifier and client nodes can use this identifier
     18  to specify the clock which they consume. All available clocks are defined as
     19  preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
     20  used in device tree sources. Similar macros exist for the reset sources in
     21  these files.
     22  There are several clocks that are generated outside the SoC. It is expected
     23  that they are defined using standard clock bindings with following
     24  clock-output-names:
     25    - "xin24m"     - crystal input                          - required
     26    - "xin32k"     - rtc clock                              - optional
     27    - "ext_i2s"    - external I2S clock                     - optional
     28    - "ext_gmac"   - external GMAC clock                    - optional
     29    - "ext_hsadc"  - external HSADC clock                   - optional
     30    - "ext_isp"    - external ISP clock                     - optional
     31    - "ext_jtag"   - external JTAG clock                    - optional
     32    - "ext_vip"    - external VIP clock                     - optional
     33    - "usbotg_out" - output clock of the pll in the otg phy
     34
     35properties:
     36  compatible:
     37    enum:
     38      - rockchip,rk3368-cru
     39
     40  reg:
     41    maxItems: 1
     42
     43  "#clock-cells":
     44    const: 1
     45
     46  "#reset-cells":
     47    const: 1
     48
     49  clocks:
     50    maxItems: 1
     51
     52  clock-names:
     53    const: xin24m
     54
     55  rockchip,grf:
     56    $ref: /schemas/types.yaml#/definitions/phandle
     57    description:
     58      Phandle to the syscon managing the "general register files" (GRF),
     59      if missing pll rates are not changeable, due to the missing pll
     60      lock status.
     61
     62required:
     63  - compatible
     64  - reg
     65  - "#clock-cells"
     66  - "#reset-cells"
     67
     68additionalProperties: false
     69
     70examples:
     71  - |
     72    cru: clock-controller@ff760000 {
     73      compatible = "rockchip,rk3368-cru";
     74      reg = <0xff760000 0x1000>;
     75      rockchip,grf = <&grf>;
     76      #clock-cells = <1>;
     77      #reset-cells = <1>;
     78    };