cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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samsung,exynos7-clock.yaml (6341B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung Exynos7 SoC clock controller
      8
      9maintainers:
     10  - Chanwoo Choi <cw00.choi@samsung.com>
     11  - Krzysztof Kozlowski <krzk@kernel.org>
     12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
     13  - Tomasz Figa <tomasz.figa@gmail.com>
     14
     15description: |
     16  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
     17  name::
     18    - "fin_pll" - PLL input clock from XXTI
     19
     20  All available clocks are defined as preprocessor macros in
     21  include/dt-bindings/clock/exynos7-clk.h header.
     22
     23properties:
     24  compatible:
     25    enum:
     26      - samsung,exynos7-clock-topc
     27      - samsung,exynos7-clock-top0
     28      - samsung,exynos7-clock-top1
     29      - samsung,exynos7-clock-ccore
     30      - samsung,exynos7-clock-peric0
     31      - samsung,exynos7-clock-peric1
     32      - samsung,exynos7-clock-peris
     33      - samsung,exynos7-clock-fsys0
     34      - samsung,exynos7-clock-fsys1
     35      - samsung,exynos7-clock-mscl
     36      - samsung,exynos7-clock-aud
     37
     38  clocks:
     39    minItems: 1
     40    maxItems: 13
     41
     42  clock-names:
     43    minItems: 1
     44    maxItems: 13
     45
     46  "#clock-cells":
     47    const: 1
     48
     49  reg:
     50    maxItems: 1
     51
     52required:
     53  - compatible
     54  - "#clock-cells"
     55  - reg
     56
     57allOf:
     58  - if:
     59      properties:
     60        compatible:
     61          contains:
     62            const: samsung,exynos7-clock-top0
     63    then:
     64      properties:
     65        clocks:
     66          minItems: 6
     67          maxItems: 6
     68        clock-names:
     69          items:
     70            - const: fin_pll
     71            - const: dout_sclk_bus0_pll
     72            - const: dout_sclk_bus1_pll
     73            - const: dout_sclk_cc_pll
     74            - const: dout_sclk_mfc_pll
     75            - const: dout_sclk_aud_pll
     76      required:
     77        - clock-names
     78        - clocks
     79
     80  - if:
     81      properties:
     82        compatible:
     83          contains:
     84            const: samsung,exynos7-clock-top1
     85    then:
     86      properties:
     87        clocks:
     88          minItems: 5
     89          maxItems: 5
     90        clock-names:
     91          items:
     92            - const: fin_pll
     93            - const: dout_sclk_bus0_pll
     94            - const: dout_sclk_bus1_pll
     95            - const: dout_sclk_cc_pll
     96            - const: dout_sclk_mfc_pll
     97      required:
     98        - clock-names
     99        - clocks
    100
    101  - if:
    102      properties:
    103        compatible:
    104          contains:
    105            const: samsung,exynos7-clock-ccore
    106    then:
    107      properties:
    108        clocks:
    109          minItems: 2
    110          maxItems: 2
    111        clock-names:
    112          items:
    113            - const: fin_pll
    114            - const: dout_aclk_ccore_133
    115      required:
    116        - clock-names
    117        - clocks
    118
    119  - if:
    120      properties:
    121        compatible:
    122          contains:
    123            const: samsung,exynos7-clock-peric0
    124    then:
    125      properties:
    126        clocks:
    127          minItems: 3
    128          maxItems: 3
    129        clock-names:
    130          items:
    131            - const: fin_pll
    132            - const: dout_aclk_peric0_66
    133            - const: sclk_uart0
    134      required:
    135        - clock-names
    136        - clocks
    137
    138  - if:
    139      properties:
    140        compatible:
    141          contains:
    142            const: samsung,exynos7-clock-peric1
    143    then:
    144      properties:
    145        clocks:
    146          minItems: 13
    147          maxItems: 13
    148        clock-names:
    149          items:
    150            - const: fin_pll
    151            - const: dout_aclk_peric1_66
    152            - const: sclk_uart1
    153            - const: sclk_uart2
    154            - const: sclk_uart3
    155            - const: sclk_spi0
    156            - const: sclk_spi1
    157            - const: sclk_spi2
    158            - const: sclk_spi3
    159            - const: sclk_spi4
    160            - const: sclk_i2s1
    161            - const: sclk_pcm1
    162            - const: sclk_spdif
    163      required:
    164        - clock-names
    165        - clocks
    166
    167  - if:
    168      properties:
    169        compatible:
    170          contains:
    171            const: samsung,exynos7-clock-peris
    172    then:
    173      properties:
    174        clocks:
    175          minItems: 2
    176          maxItems: 2
    177        clock-names:
    178          items:
    179            - const: fin_pll
    180            - const: dout_aclk_peris_66
    181      required:
    182        - clock-names
    183        - clocks
    184
    185  - if:
    186      properties:
    187        compatible:
    188          contains:
    189            const: samsung,exynos7-clock-fsys0
    190    then:
    191      properties:
    192        clocks:
    193          minItems: 3
    194          maxItems: 3
    195        clock-names:
    196          items:
    197            - const: fin_pll
    198            - const: dout_aclk_fsys0_200
    199            - const: dout_sclk_mmc2
    200      required:
    201        - clock-names
    202        - clocks
    203
    204  - if:
    205      properties:
    206        compatible:
    207          contains:
    208            const: samsung,exynos7-clock-fsys1
    209    then:
    210      properties:
    211        clocks:
    212          minItems: 7
    213          maxItems: 7
    214        clock-names:
    215          items:
    216            - const: fin_pll
    217            - const: dout_aclk_fsys1_200
    218            - const: dout_sclk_mmc0
    219            - const: dout_sclk_mmc1
    220            - const: dout_sclk_ufsunipro20
    221            - const: dout_sclk_phy_fsys1
    222            - const: dout_sclk_phy_fsys1_26m
    223      required:
    224        - clock-names
    225        - clocks
    226
    227  - if:
    228      properties:
    229        compatible:
    230          contains:
    231            const: samsung,exynos7-clock-aud
    232    then:
    233      properties:
    234        clocks:
    235          minItems: 2
    236          maxItems: 2
    237        clock-names:
    238          items:
    239            - const: fin_pll
    240            - const: fout_aud_pll
    241      required:
    242        - clock-names
    243        - clocks
    244
    245additionalProperties: false
    246
    247examples:
    248  - |
    249    #include <dt-bindings/clock/exynos7-clk.h>
    250
    251    fin_pll: clock {
    252        compatible = "fixed-clock";
    253        clock-output-names = "fin_pll";
    254        #clock-cells = <0>;
    255        clock-frequency = <24000000>;
    256    };
    257
    258    clock-controller@105e0000 {
    259        compatible = "samsung,exynos7-clock-top1";
    260        reg = <0x105e0000 0xb000>;
    261        #clock-cells = <1>;
    262        clocks = <&fin_pll>,
    263                 <&clock_topc DOUT_SCLK_BUS0_PLL>,
    264                 <&clock_topc DOUT_SCLK_BUS1_PLL>,
    265                 <&clock_topc DOUT_SCLK_CC_PLL>,
    266                 <&clock_topc DOUT_SCLK_MFC_PLL>;
    267        clock-names = "fin_pll",
    268                      "dout_sclk_bus0_pll",
    269                      "dout_sclk_bus1_pll",
    270                      "dout_sclk_cc_pll",
    271                      "dout_sclk_mfc_pll";
    272    };