cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung,s3c2412-clock.txt (1625B)


      1* Samsung S3C2412 Clock Controller
      2
      3The S3C2412 clock controller generates and supplies clock to various controllers
      4within the SoC. The clock binding described here is applicable to the s3c2412
      5and s3c2413 SoCs in the s3c24x family.
      6
      7Required Properties:
      8
      9- compatible: should be "samsung,s3c2412-clock"
     10- reg: physical base address of the controller and length of memory mapped
     11  region.
     12- #clock-cells: should be 1.
     13
     14Each clock is assigned an identifier and client nodes can use this identifier
     15to specify the clock which they consume. Some of the clocks are available only
     16on a particular SoC.
     17
     18All available clocks are defined as preprocessor macros in
     19dt-bindings/clock/s3c2412.h header and can be used in device
     20tree sources.
     21
     22External clocks:
     23
     24There are several clocks that are generated outside the SoC. It is expected
     25that they are defined using standard clock bindings with following
     26clock-output-names:
     27 - "xti" - crystal input - required,
     28 - "ext" - external clock source - optional,
     29
     30Example: Clock controller node:
     31
     32	clocks: clock-controller@4c000000 {
     33		compatible = "samsung,s3c2412-clock";
     34		reg = <0x4c000000 0x20>;
     35		#clock-cells = <1>;
     36	};
     37
     38Example: UART controller node that consumes the clock generated by the clock
     39  controller (refer to the standard clock bindings for information about
     40  "clocks" and "clock-names" properties):
     41
     42	serial@50004000 {
     43		compatible = "samsung,s3c2412-uart";
     44		reg = <0x50004000 0x4000>;
     45		interrupts = <1 23 3 4>, <1 23 4 4>;
     46		clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
     47		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
     48			 <&clocks SCLK_UART>;
     49	};