cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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silabs,si5351.txt (3834B)


      1Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
      2
      3Reference
      4[1] Si5351A/B/C Data Sheet
      5    https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
      6
      7The Si5351a/b/c are programmable i2c clock generators with up to 8 output
      8clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
      93 output clocks are accessible. The internal structure of the clock
     10generators can be found in [1].
     11
     12==I2C device node==
     13
     14Required properties:
     15- compatible: shall be one of the following:
     16	"silabs,si5351a" - Si5351a, QFN20 package
     17	"silabs,si5351a-msop" - Si5351a, MSOP10 package
     18	"silabs,si5351b" - Si5351b, QFN20 package
     19	"silabs,si5351c" - Si5351c, QFN20 package
     20- reg: i2c device address, shall be 0x60 or 0x61.
     21- #clock-cells: from common clock binding; shall be set to 1.
     22- clocks: from common clock binding; list of parent clock
     23  handles, shall be xtal reference clock or xtal and clkin for
     24  si5351c only. Corresponding clock input names are "xtal" and
     25  "clkin" respectively.
     26- #address-cells: shall be set to 1.
     27- #size-cells: shall be set to 0.
     28
     29Optional properties:
     30- silabs,pll-source: pair of (number, source) for each pll. Allows
     31  to overwrite clock source of pll A (number=0) or B (number=1).
     32
     33==Child nodes==
     34
     35Each of the clock outputs can be overwritten individually by
     36using a child node to the I2C device node. If a child node for a clock
     37output is not set, the eeprom configuration is not overwritten.
     38
     39Required child node properties:
     40- reg: number of clock output.
     41
     42Optional child node properties:
     43- silabs,clock-source: source clock of the output divider stage N, shall be
     44  0 = multisynth N
     45  1 = multisynth 0 for output clocks 0-3, else multisynth4
     46  2 = xtal
     47  3 = clkin (si5351c only)
     48- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
     49- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
     50  divider.
     51- silabs,pll-master: boolean, multisynth can change pll frequency.
     52- silabs,pll-reset: boolean, clock output can reset its pll.
     53- silabs,disable-state : clock output disable state, shall be
     54  0 = clock output is driven LOW when disabled
     55  1 = clock output is driven HIGH when disabled
     56  2 = clock output is FLOATING (HIGH-Z) when disabled
     57  3 = clock output is NEVER disabled
     58
     59==Example==
     60
     61/* 25MHz reference crystal */
     62ref25: ref25M {
     63	compatible = "fixed-clock";
     64	#clock-cells = <0>;
     65	clock-frequency = <25000000>;
     66};
     67
     68i2c-master-node {
     69
     70	/* Si5351a msop10 i2c clock generator */
     71	si5351a: clock-generator@60 {
     72		compatible = "silabs,si5351a-msop";
     73		reg = <0x60>;
     74		#address-cells = <1>;
     75		#size-cells = <0>;
     76		#clock-cells = <1>;
     77
     78		/* connect xtal input to 25MHz reference */
     79		clocks = <&ref25>;
     80		clock-names = "xtal";
     81
     82		/* connect xtal input as source of pll0 and pll1 */
     83		silabs,pll-source = <0 0>, <1 0>;
     84
     85		/*
     86		 * overwrite clkout0 configuration with:
     87		 * - 8mA output drive strength
     88		 * - pll0 as clock source of multisynth0
     89		 * - multisynth0 as clock source of output divider
     90		 * - multisynth0 can change pll0
     91		 * - set initial clock frequency of 74.25MHz
     92		 */
     93		clkout0 {
     94			reg = <0>;
     95			silabs,drive-strength = <8>;
     96			silabs,multisynth-source = <0>;
     97			silabs,clock-source = <0>;
     98			silabs,pll-master;
     99			clock-frequency = <74250000>;
    100		};
    101
    102		/*
    103		 * overwrite clkout1 configuration with:
    104		 * - 4mA output drive strength
    105		 * - pll1 as clock source of multisynth1
    106		 * - multisynth1 as clock source of output divider
    107		 * - multisynth1 can change pll1
    108		 */
    109		clkout1 {
    110			reg = <1>;
    111			silabs,drive-strength = <4>;
    112			silabs,multisynth-source = <1>;
    113			silabs,clock-source = <0>;
    114			pll-master;
    115		};
    116
    117		/*
    118		 * overwrite clkout2 configuration with:
    119		 * - xtal as clock source of output divider
    120		 */
    121		clkout2 {
    122			reg = <2>;
    123			silabs,clock-source = <2>;
    124		};
    125	};
    126};