cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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snps,hsdk-pll-clock.txt (762B)


      1Binding for the HSDK Generic PLL clock
      2
      3This binding uses the common clock binding[1].
      4
      5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
      6
      7Required properties:
      8- compatible: should be "snps,hsdk-<name>-pll-clock"
      9  "snps,hsdk-core-pll-clock"
     10  "snps,hsdk-gp-pll-clock"
     11  "snps,hsdk-hdmi-pll-clock"
     12- reg : should contain base register location and length.
     13- clocks: shall be the input parent clock phandle for the PLL.
     14- #clock-cells: from common clock binding; Should always be set to 0.
     15
     16Example:
     17	input_clk: input-clk {
     18		clock-frequency = <33333333>;
     19		compatible = "fixed-clock";
     20		#clock-cells = <0>;
     21	};
     22
     23	cpu_clk: cpu-clk@0 {
     24		compatible = "snps,hsdk-core-pll-clock";
     25		reg = <0x00 0x10>;
     26		#clock-cells = <0>;
     27		clocks = <&input_clk>;
     28	};