cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stm32h7-rcc.txt (2023B)

      1STMicroelectronics STM32H7 Reset and Clock Controller
      2=====================================================
      3
      4The RCC IP is both a reset and a clock controller.
      5
      6Please refer to clock-bindings.txt for common clock controller binding usage.
      7Please also refer to reset.txt for common reset controller binding usage.
      8
      9Required properties:
     10- compatible: Should be:
     11  "st,stm32h743-rcc"
     12
     13- reg: should be register base and length as documented in the
     14  datasheet
     15
     16- #reset-cells: 1, see below
     17
     18- #clock-cells : from common clock binding; shall be set to 1
     19
     20- clocks: External oscillator clock phandle
     21  - high speed external clock signal (HSE)
     22  - low speed external clock signal (LSE)
     23  - external I2S clock (I2S_CKIN)
     24
     25Optional properties:
     26- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
     27  write protection (RTC clock).
     28
     29Example:
     30
     31	rcc: reset-clock-controller@58024400 {
     32		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
     33		reg = <0x58024400 0x400>;
     34		#reset-cells = <1>;
     35		#clock-cells = <1>;
     36		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
     37
     38		st,syscfg = <&pwrcfg>;
     39};
     40
     41The peripheral clock consumer should specify the desired clock by
     42having the clock ID in its "clocks" phandle cell.
     43
     44Example:
     45
     46		timer5: timer@40000c00 {
     47			compatible = "st,stm32-timer";
     48			reg = <0x40000c00 0x400>;
     49			interrupts = <50>;
     50			clocks = <&rcc TIM5_CK>;
     51		};
     52
     53Specifying softreset control of devices
     54=======================================
     55
     56Device nodes should specify the reset channel required in their "resets"
     57property, containing a phandle to the reset device node and an index specifying
     58which channel to use.
     59The index is the bit number within the RCC registers bank, starting from RCC
     60base address.
     61It is calculated as: index = register_offset / 4 * 32 + bit_offset.
     62Where bit_offset is the bit offset within the register.
     63
     64For example, for CRC reset:
     65  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
     66
     67Example:
     68
     69	timer2 {
     70		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;
     71	};