ti,cdce925.txt (1751B)
1Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers. 2 3Reference 4This binding uses the common clock binding[1]. 5 6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 7[2] https://www.ti.com/product/cdce913 8[3] https://www.ti.com/product/cdce925 9[4] https://www.ti.com/product/cdce937 10[5] https://www.ti.com/product/cdce949 11 12The driver provides clock sources for each output Y1 through Y5. 13 14Required properties: 15 - compatible: Shall be one of the following: 16 - "ti,cdce913": 1-PLL, 3 Outputs 17 - "ti,cdce925": 2-PLL, 5 Outputs 18 - "ti,cdce937": 3-PLL, 7 Outputs 19 - "ti,cdce949": 4-PLL, 9 Outputs 20 - reg: I2C device address. 21 - clocks: Points to a fixed parent clock that provides the input frequency. 22 - #clock-cells: From common clock bindings: Shall be 1. 23 24Optional properties: 25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a 26 board, or to compensate for external influences. 27- vdd-supply: A regulator node for Vdd 28- vddout-supply: A regulator node for Vddout 29 30For all PLL1, PLL2, ... an optional child node can be used to specify spread 31spectrum clocking parameters for a board. 32 - spread-spectrum: SSC mode as defined in the data sheet. 33 - spread-spectrum-center: Use "centered" mode instead of "max" mode. When 34 present, the clock runs at the requested frequency on average. Otherwise 35 the requested frequency is the maximum value of the SCC range. 36 37 38Example: 39 40 clockgen: cdce925pw@64 { 41 compatible = "cdce925"; 42 reg = <0x64>; 43 clocks = <&xtal_27Mhz>; 44 #clock-cells = <1>; 45 xtal-load-pf = <5>; 46 vdd-supply = <&1v8-reg>; 47 vddout-supply = <&3v3-reg>; 48 /* PLL options to get SSC 1% centered */ 49 PLL2 { 50 spread-spectrum = <4>; 51 spread-spectrum-center; 52 }; 53 };