cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fapll.txt (1068B)


      1Binding for Texas Instruments FAPLL clock.
      2
      3Binding status: Unstable - ABI compatibility may be broken in the future
      4
      5This binding uses the common clock binding[1]. It assumes a
      6register-mapped FAPLL with usually two selectable input clocks
      7(reference clock and bypass clock), and one or more child
      8syntesizers.
      9
     10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
     11
     12Required properties:
     13- compatible : shall be "ti,dm816-fapll-clock"
     14- #clock-cells : from common clock binding; shall be set to 0.
     15- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
     16- reg : address and length of the register set for controlling the FAPLL.
     17
     18Examples:
     19	main_fapll: main_fapll {
     20		#clock-cells = <1>;
     21		compatible = "ti,dm816-fapll-clock";
     22		reg = <0x400 0x40>;
     23		clocks = <&sys_clkin_ck &sys_clkin_ck>;
     24		clock-indices = <1>, <2>, <3>, <4>, <5>,
     25				<6>, <7>;
     26		clock-output-names = "main_pll_clk1",
     27				     "main_pll_clk2",
     28				     "main_pll_clk3",
     29				     "main_pll_clk4",
     30				     "main_pll_clk5",
     31				     "main_pll_clk6",
     32				     "main_pll_clk7";
     33	};