cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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vf610-clock.txt (1211B)


      1* Clock bindings for Freescale Vybrid VF610 SOC
      2
      3Required properties:
      4- compatible: Should be "fsl,vf610-ccm"
      5- reg: Address and length of the register set
      6- #clock-cells: Should be <1>
      7
      8Optional properties:
      9- clocks: list of clock identifiers which are external input clocks to the
     10	given clock controller. Please refer the next section to find
     11	the input clocks for a given controller.
     12- clock-names: list of names of clocks which are exteral input clocks to the
     13	given clock controller.
     14
     15Input clocks for top clock controller:
     16	- sxosc (external crystal oscillator 32KHz, recommended)
     17	- fxosc (external crystal oscillator 24MHz, recommended)
     18	- audio_ext
     19	- enet_ext
     20
     21The clock consumer should specify the desired clock by having the clock
     22ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
     23for the full list of VF610 clock IDs.
     24
     25Examples:
     26
     27clks: ccm@4006b000 {
     28	compatible = "fsl,vf610-ccm";
     29	reg = <0x4006b000 0x1000>;
     30	#clock-cells = <1>;
     31	clocks = <&sxosc>, <&fxosc>;
     32	clock-names = "sxosc", "fxosc";
     33};
     34
     35uart1: serial@40028000 {
     36	compatible = "fsl,vf610-uart";
     37	reg = <0x40028000 0x1000>;
     38	interrupts = <0 62 0x04>;
     39	clocks = <&clks VF610_CLK_UART1>;
     40	clock-names = "ipg";
     41};