cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,stb-avs-cpu-freq.txt (2524B)

      1Broadcom AVS mail box and interrupt register bindings
      2=====================================================
      3
      4A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
      5references the mailbox register used to communicate with the AVS CPU[1]. The
      6second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
      7the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
      8command sent to it by a driver. Interrupting the AVS CPU is mandatory for
      9commands to be processed.
     10
     11The interface also requires a reference to the AVS host interrupt controller,
     12so a driver can react to interrupts generated by the AVS CPU whenever a command
     13has been processed. See [2] for more information on the brcm,l2-intc node.
     14
     15[1] The AVS CPU is an independent co-processor that runs proprietary
     16firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
     17Adaptive Voltage Scaling.
     18
     19[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
     20
     21
     22Node brcm,avs-cpu-data-mem
     23--------------------------
     24
     25Required properties:
     26- compatible: must include: brcm,avs-cpu-data-mem and
     27              should include: one of brcm,bcm7271-avs-cpu-data-mem or
     28                              brcm,bcm7268-avs-cpu-data-mem
     29- reg: Specifies base physical address and size of the registers.
     30- interrupts: The interrupt that the AVS CPU will use to interrupt the host
     31              when a command completed.
     32- interrupt-names: The name of the interrupt used to interrupt the host.
     33
     34Optional properties:
     35- None
     36
     37Node brcm,avs-cpu-l2-intr
     38-------------------------
     39
     40Required properties:
     41- compatible: must include: brcm,avs-cpu-l2-intr and
     42              should include: one of brcm,bcm7271-avs-cpu-l2-intr or
     43                              brcm,bcm7268-avs-cpu-l2-intr
     44- reg: Specifies base physical address and size of the registers.
     45
     46Optional properties:
     47- None
     48
     49
     50Example
     51=======
     52
     53	avs_host_l2_intc: interrupt-controller@f04d1200 {
     54		#interrupt-cells = <1>;
     55		compatible = "brcm,l2-intc";
     56		interrupt-parent = <&intc>;
     57		reg = <0xf04d1200 0x48>;
     58		interrupt-controller;
     59		interrupts = <0x0 0x19 0x0>;
     60		interrupt-names = "avs";
     61	};
     62
     63	avs-cpu-data-mem@f04c4000 {
     64		compatible = "brcm,bcm7271-avs-cpu-data-mem",
     65				"brcm,avs-cpu-data-mem";
     66		reg = <0xf04c4000 0x60>;
     67		interrupts = <0x1a>;
     68		interrupt-parent = <&avs_host_l2_intc>;
     69		interrupt-names = "sw_intr";
     70	};
     71
     72	avs-cpu-l2-intr@f04d1100 {
     73		compatible = "brcm,bcm7271-avs-cpu-l2-intr",
     74				"brcm,avs-cpu-l2-intr";
     75		reg = <0xf04d1100 0x10>;
     76	};