cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpufreq-st.txt (2402B)

      1Binding for ST's CPUFreq driver
      2===============================
      3
      4ST's CPUFreq driver attempts to read 'process' and 'version' attributes
      5from the SoC, then supplies the OPP framework with 'prop' and 'supported
      6hardware' information respectively.  The framework is then able to read
      7the DT and operate in the usual way.
      8
      9Frequency Scaling only
     10----------------------
     11
     12No vendor specific driver required for this.
     13
     14Located in CPU's node:
     15
     16- operating-points		: [See: ../power/opp-v1.yaml]
     17
     18Example [safe]
     19--------------
     20
     21cpus {
     22	cpu@0 {
     23				 /* kHz     uV   */
     24		operating-points = <1500000 0
     25				    1200000 0
     26				    800000  0
     27				    500000  0>;
     28	};
     29};
     30
     31Dynamic Voltage and Frequency Scaling (DVFS)
     32--------------------------------------------
     33
     34This requires the ST CPUFreq driver to supply 'process' and 'version' info.
     35
     36Located in CPU's node:
     37
     38- operating-points-v2		: [See ../power/opp-v2.yaml]
     39
     40Example [unsafe]
     41----------------
     42
     43cpus {
     44	cpu@0 {
     45		operating-points-v2	= <&cpu0_opp_table>;
     46	};
     47};
     48
     49cpu0_opp_table: opp_table {
     50	compatible = "operating-points-v2";
     51
     52	/* ############################################################### */
     53	/* # WARNING: Do not attempt to copy/replicate these nodes,      # */
     54	/* #          they are only to be supplied by the bootloader !!! # */
     55	/* ############################################################### */
     56	opp0 {
     57		/*			   Major       Minor       Substrate */
     58		/*			   2           all         all       */
     59		opp-supported-hw	= <0x00000004  0xffffffff  0xffffffff>;
     60		opp-hz			= /bits/ 64 <1500000000>;
     61		clock-latency-ns	= <10000000>;
     62
     63		opp-microvolt-pcode0	= <1200000>;
     64		opp-microvolt-pcode1	= <1200000>;
     65		opp-microvolt-pcode2	= <1200000>;
     66		opp-microvolt-pcode3	= <1200000>;
     67		opp-microvolt-pcode4	= <1170000>;
     68		opp-microvolt-pcode5	= <1140000>;
     69		opp-microvolt-pcode6	= <1100000>;
     70		opp-microvolt-pcode7	= <1070000>;
     71	};
     72
     73	opp1 {
     74		/*			   Major       Minor       Substrate */
     75		/*			   all         all         all       */
     76		opp-supported-hw	= <0xffffffff  0xffffffff  0xffffffff>;
     77		opp-hz			= /bits/ 64 <1200000000>;
     78		clock-latency-ns	= <10000000>;
     79
     80		opp-microvolt-pcode0	= <1110000>;
     81		opp-microvolt-pcode1	= <1150000>;
     82		opp-microvolt-pcode2	= <1100000>;
     83		opp-microvolt-pcode3	= <1080000>;
     84		opp-microvolt-pcode4	= <1040000>;
     85		opp-microvolt-pcode5	= <1020000>;
     86		opp-microvolt-pcode6	= <980000>;
     87		opp-microvolt-pcode7	= <930000>;
     88	};
     89};