cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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atmel,at91sam9g46-sha.yaml (1284B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
      3%YAML 1.2
      4---
      5$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
      6$schema: http://devicetree.org/meta-schemas/core.yaml#
      7
      8title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
      9
     10maintainers:
     11  - Tudor Ambarus <tudor.ambarus@microchip.com>
     12
     13properties:
     14  compatible:
     15    const: atmel,at91sam9g46-sha
     16
     17  reg:
     18    maxItems: 1
     19
     20  interrupts:
     21    maxItems: 1
     22
     23  clocks:
     24    maxItems: 1
     25
     26  clock-names:
     27    const: sha_clk
     28
     29  dmas:
     30    maxItems: 1
     31    description: TX DMA Channel
     32
     33  dma-names:
     34    const: tx
     35
     36required:
     37  - compatible
     38  - reg
     39  - interrupts
     40  - clocks
     41  - clock-names
     42
     43additionalProperties: false
     44
     45examples:
     46  - |
     47    #include <dt-bindings/interrupt-controller/irq.h>
     48    #include <dt-bindings/interrupt-controller/arm-gic.h>
     49    #include <dt-bindings/clock/at91.h>
     50    #include <dt-bindings/dma/at91.h>
     51
     52    sha: crypto@e1814000 {
     53      compatible = "atmel,at91sam9g46-sha";
     54      reg = <0xe1814000 0x100>;
     55      interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
     56      clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
     57      clock-names = "sha_clk";
     58      dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
     59      dma-names = "tx";
     60    };