fsl-sec2.txt (2787B)
1Freescale SoC SEC Security Engines versions 1.x-2.x-3.x 2 3Required properties: 4 5- compatible : Should contain entries for this and backward compatible 6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) 7 e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) 8 warning: SEC1 and SEC2 are mutually exclusive 9- reg : Offset and length of the register set for the device 10- interrupts : the SEC's interrupt number 11- fsl,num-channels : An integer representing the number of channels 12 available. 13- fsl,channel-fifo-len : An integer representing the number of 14 descriptor pointers each channel fetch fifo can hold. 15- fsl,exec-units-mask : The bitmask representing what execution units 16 (EUs) are available. It's a single 32-bit cell. EU information 17 should be encoded following the SEC's Descriptor Header Dword 18 EU_SEL0 field documentation, i.e. as follows: 19 20 bit 0 = reserved - should be 0 21 bit 1 = set if SEC has the ARC4 EU (AFEU) 22 bit 2 = set if SEC has the DES/3DES EU (DEU) 23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) 24 bit 4 = set if SEC has the random number generator EU (RNG) 25 bit 5 = set if SEC has the public key EU (PKEU) 26 bit 6 = set if SEC has the AES EU (AESU) 27 bit 7 = set if SEC has the Kasumi EU (KEU) 28 bit 8 = set if SEC has the CRC EU (CRCU) 29 bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) 30 31remaining bits are reserved for future SEC EUs. 32 33- fsl,descriptor-types-mask : The bitmask representing what descriptors 34 are available. It's a single 32-bit cell. Descriptor type information 35 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE 36 field documentation, i.e. as follows: 37 38 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type 39 bit 1 = set if SEC supports the ipsec_esp descriptor type 40 bit 2 = set if SEC supports the common_nonsnoop desc. type 41 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type 42 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type 43 bit 5 = set if SEC supports the srtp descriptor type 44 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type 45 bit 7 = set if SEC supports the pkeu_assemble descriptor type 46 bit 8 = set if SEC supports the aesu_key_expand_output desc.type 47 bit 9 = set if SEC supports the pkeu_ptmul descriptor type 48 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type 49 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type 50 51 ..and so on and so forth. 52 53Example: 54 55 /* MPC8548E */ 56 crypto@30000 { 57 compatible = "fsl,sec2.1", "fsl,sec2.0"; 58 reg = <0x30000 0x10000>; 59 interrupts = <29 2>; 60 interrupt-parent = <&mpic>; 61 fsl,num-channels = <4>; 62 fsl,channel-fifo-len = <24>; 63 fsl,exec-units-mask = <0xfe>; 64 fsl,descriptor-types-mask = <0x12b0ebf>; 65 };