cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stm32-hash.yaml (1315B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: STMicroelectronics STM32 HASH bindings
      8
      9maintainers:
     10  - Lionel Debieve <lionel.debieve@foss.st.com>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - st,stm32f456-hash
     16      - st,stm32f756-hash
     17
     18  reg:
     19    maxItems: 1
     20
     21  clocks:
     22    maxItems: 1
     23
     24  interrupts:
     25    maxItems: 1
     26
     27  resets:
     28    maxItems: 1
     29
     30  dmas:
     31    maxItems: 1
     32
     33  dma-names:
     34    items:
     35      - const: in
     36
     37  dma-maxburst:
     38    description: Set number of maximum dma burst supported
     39    $ref: /schemas/types.yaml#/definitions/uint32
     40    minimum: 0
     41    maximum: 2
     42    default: 0
     43
     44required:
     45  - compatible
     46  - reg
     47  - clocks
     48  - interrupts
     49
     50additionalProperties: false
     51
     52examples:
     53  - |
     54    #include <dt-bindings/interrupt-controller/arm-gic.h>
     55    #include <dt-bindings/clock/stm32mp1-clks.h>
     56    #include <dt-bindings/reset/stm32mp1-resets.h>
     57    hash@54002000 {
     58      compatible = "st,stm32f756-hash";
     59      reg = <0x54002000 0x400>;
     60      interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
     61      clocks = <&rcc HASH1>;
     62      resets = <&rcc HASH1_R>;
     63      dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
     64      dma-names = "in";
     65      dma-maxburst = <2>;
     66    };
     67
     68...