cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arm,komeda.yaml (2865B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Arm Komeda display processor
      8
      9maintainers:
     10  - Liviu Dudau <Liviu.Dudau@arm.com>
     11  - Andre Przywara <andre.przywara@arm.com>
     12
     13description:
     14  The Arm Mali D71 display processor supports up to two displays with up
     15  to a 4K resolution each. Each pipeline can be composed of up to four
     16  layers. It is typically connected to a digital display connector like HDMI.
     17
     18properties:
     19  compatible:
     20    oneOf:
     21      - items:
     22          - const: arm,mali-d32
     23          - const: arm,mali-d71
     24      - const: arm,mali-d71
     25
     26  reg:
     27    maxItems: 1
     28
     29  interrupts:
     30    maxItems: 1
     31
     32  clock-names:
     33    const: aclk
     34
     35  clocks:
     36    maxItems: 1
     37    description: The main DPU processor clock
     38
     39  "#address-cells":
     40    const: 1
     41
     42  "#size-cells":
     43    const: 0
     44
     45  memory-region:
     46    maxItems: 1
     47    description:
     48      Phandle to a node describing memory to be used for the framebuffer.
     49      If not present, the framebuffer may be located anywhere in memory.
     50
     51  iommus:
     52    description:
     53      The stream IDs for each of the used pipelines, each four IDs for the
     54      four layers, plus one for the write-back stream.
     55    minItems: 5
     56    maxItems: 10
     57
     58patternProperties:
     59  '^pipeline@[01]$':
     60    type: object
     61    description:
     62      clocks
     63
     64    properties:
     65      reg:
     66        enum: [ 0, 1 ]
     67
     68      clock-names:
     69        const: pxclk
     70
     71      clocks:
     72        maxItems: 1
     73        description: The input reference for the pixel clock.
     74
     75      port:
     76        $ref: /schemas/graph.yaml#/$defs/port-base
     77        unevaluatedProperties: false
     78
     79additionalProperties: false
     80
     81required:
     82  - "#address-cells"
     83  - "#size-cells"
     84  - compatible
     85  - reg
     86  - interrupts
     87  - clock-names
     88  - clocks
     89  - pipeline@0
     90
     91examples:
     92  - |
     93    display@c00000 {
     94        #address-cells = <1>;
     95        #size-cells = <0>;
     96        compatible = "arm,mali-d71";
     97        reg = <0xc00000 0x20000>;
     98        interrupts = <168>;
     99        clocks = <&dpu_aclk>;
    100        clock-names = "aclk";
    101        iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
    102                 <&smmu 8>,
    103                 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
    104                 <&smmu 9>;
    105
    106        dp0_pipe0: pipeline@0 {
    107            clocks = <&fpgaosc2>;
    108            clock-names = "pxclk";
    109            reg = <0>;
    110
    111            port {
    112                dp0_pipe0_out: endpoint {
    113                    remote-endpoint = <&db_dvi0_in>;
    114                };
    115            };
    116        };
    117
    118        dp0_pipe1: pipeline@1 {
    119            clocks = <&fpgaosc2>;
    120            clock-names = "pxclk";
    121            reg = <1>;
    122
    123            port {
    124                dp0_pipe1_out: endpoint {
    125                    remote-endpoint = <&db_dvi1_in>;
    126                };
    127            };
    128        };
    129    };
    130...