cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cdns,mhdp8546.yaml (3800B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Cadence MHDP8546 bridge
      8
      9maintainers:
     10  - Swapnil Jakhade <sjakhade@cadence.com>
     11  - Yuti Amonkar <yamonkar@cadence.com>
     12
     13properties:
     14  compatible:
     15    enum:
     16      - cdns,mhdp8546
     17      - ti,j721e-mhdp8546
     18
     19  reg:
     20    minItems: 1
     21    items:
     22      - description:
     23          Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
     24          The AUX and PMA registers are not part of this range, they are instead
     25          included in the associated PHY.
     26      - description:
     27          Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
     28      - description:
     29          Register block of mhdptx sapb registers.
     30
     31  reg-names:
     32    minItems: 1
     33    items:
     34      - const: mhdptx
     35      - const: j721e-intg
     36      - const: mhdptx-sapb
     37
     38  clocks:
     39    maxItems: 1
     40    description:
     41      DP bridge clock, used by the IP to know how to translate a number of
     42      clock cycles into a time (which is used to comply with DP standard timings
     43      and delays).
     44
     45  phys:
     46    maxItems: 1
     47    description:
     48      phandle to the DisplayPort PHY.
     49
     50  phy-names:
     51    items:
     52      - const: dpphy
     53
     54  power-domains:
     55    maxItems: 1
     56
     57  interrupts:
     58    maxItems: 1
     59
     60  ports:
     61    $ref: /schemas/graph.yaml#/properties/ports
     62
     63    properties:
     64      port@0:
     65        $ref: /schemas/graph.yaml#/properties/port
     66        description:
     67          First input port representing the DP bridge input.
     68
     69      port@1:
     70        $ref: /schemas/graph.yaml#/properties/port
     71        description:
     72          Second input port representing the DP bridge input.
     73
     74      port@2:
     75        $ref: /schemas/graph.yaml#/properties/port
     76        description:
     77          Third input port representing the DP bridge input.
     78
     79      port@3:
     80        $ref: /schemas/graph.yaml#/properties/port
     81        description:
     82          Fourth input port representing the DP bridge input.
     83
     84      port@4:
     85        $ref: /schemas/graph.yaml#/properties/port
     86        description:
     87          Output port representing the DP bridge output.
     88
     89    required:
     90      - port@0
     91      - port@4
     92
     93allOf:
     94  - if:
     95      properties:
     96        compatible:
     97          contains:
     98            const: ti,j721e-mhdp8546
     99    then:
    100      properties:
    101        reg:
    102          minItems: 2
    103          maxItems: 3
    104        reg-names:
    105          minItems: 2
    106          maxItems: 3
    107    else:
    108      properties:
    109        reg:
    110          minItems: 1
    111          maxItems: 2
    112        reg-names:
    113          minItems: 1
    114          maxItems: 2
    115
    116required:
    117  - compatible
    118  - clocks
    119  - reg
    120  - reg-names
    121  - phys
    122  - phy-names
    123  - interrupts
    124  - ports
    125
    126additionalProperties: false
    127
    128examples:
    129  - |
    130    #include <dt-bindings/interrupt-controller/arm-gic.h>
    131    bus {
    132        #address-cells = <2>;
    133        #size-cells = <2>;
    134
    135        mhdp: dp-bridge@f0fb000000 {
    136            compatible = "cdns,mhdp8546";
    137            reg = <0xf0 0xfb000000 0x0 0x1000000>;
    138            reg-names = "mhdptx";
    139            clocks = <&mhdp_clock>;
    140            phys = <&dp_phy>;
    141            phy-names = "dpphy";
    142            interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
    143
    144            ports {
    145                #address-cells = <1>;
    146                #size-cells = <0>;
    147
    148                port@0 {
    149                    reg = <0>;
    150                    dp_bridge_input: endpoint {
    151                        remote-endpoint = <&xxx_dpi_output>;
    152                    };
    153                };
    154
    155                port@4 {
    156                    reg = <4>;
    157                    dp_bridge_output: endpoint {
    158                        remote-endpoint = <&xxx_dp_connector_input>;
    159                    };
    160                };
    161            };
    162        };
    163    };
    164...