cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,ldb.yaml (2101B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale i.MX8MP DPI to LVDS bridge chip
      8
      9maintainers:
     10  - Marek Vasut <marex@denx.de>
     11
     12description: |
     13  The i.MX8MP mediamix contains two registers which are responsible
     14  for configuring the on-SoC DPI-to-LVDS serializer. This describes
     15  those registers as bridge within the DT.
     16
     17properties:
     18  compatible:
     19    const: fsl,imx8mp-ldb
     20
     21  clocks:
     22    maxItems: 1
     23
     24  clock-names:
     25    const: ldb
     26
     27  ports:
     28    $ref: /schemas/graph.yaml#/properties/ports
     29
     30    properties:
     31      port@0:
     32        $ref: /schemas/graph.yaml#/properties/port
     33        description: Video port for DPI input.
     34
     35      port@1:
     36        $ref: /schemas/graph.yaml#/properties/port
     37        description: Video port for LVDS Channel-A output (panel or bridge).
     38
     39      port@2:
     40        $ref: /schemas/graph.yaml#/properties/port
     41        description: Video port for LVDS Channel-B output (panel or bridge).
     42
     43    required:
     44      - port@0
     45      - port@1
     46
     47required:
     48  - compatible
     49  - clocks
     50  - ports
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/clock/imx8mp-clock.h>
     57
     58    blk-ctrl {
     59        bridge {
     60            compatible = "fsl,imx8mp-ldb";
     61            clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
     62            clock-names = "ldb";
     63
     64            ports {
     65                #address-cells = <1>;
     66                #size-cells = <0>;
     67
     68                port@0 {
     69                    reg = <0>;
     70
     71                    ldb_from_lcdif2: endpoint {
     72                        remote-endpoint = <&lcdif2_to_ldb>;
     73                    };
     74                };
     75
     76                port@1 {
     77                    reg = <1>;
     78
     79                    ldb_lvds_ch0: endpoint {
     80                        remote-endpoint = <&ldb_to_lvdsx4panel>;
     81                    };
     82                };
     83
     84                port@2 {
     85                    reg = <2>;
     86
     87                    ldb_lvds_ch1: endpoint {
     88                    };
     89                };
     90            };
     91        };
     92    };