cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl-imx-drm.txt (4350B)

      1Freescale i.MX DRM master device
      2================================
      3
      4The freescale i.MX DRM master device is a virtual device needed to list all
      5IPU or other display interface nodes that comprise the graphics subsystem.
      6
      7Required properties:
      8- compatible: Should be "fsl,imx-display-subsystem"
      9- ports: Should contain a list of phandles pointing to display interface ports
     10  of IPU devices
     11
     12example:
     13
     14display-subsystem {
     15	compatible = "fsl,imx-display-subsystem";
     16	ports = <&ipu_di0>;
     17};
     18
     19
     20Freescale i.MX IPUv3
     21====================
     22
     23Required properties:
     24- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
     25  - imx51
     26  - imx53
     27  - imx6q
     28  - imx6qp
     29- reg: should be register base and length as documented in the
     30  datasheet
     31- interrupts: Should contain sync interrupt and error interrupt,
     32  in this order.
     33- resets: phandle pointing to the system reset controller and
     34          reset line index, see reset/fsl,imx-src.txt for details
     35Additional required properties for fsl,imx6qp-ipu:
     36- fsl,prg: phandle to prg node associated with this IPU instance
     37Optional properties:
     38- port@[0-3]: Port nodes with endpoint definitions as defined in
     39  Documentation/devicetree/bindings/media/video-interfaces.txt.
     40  Ports 0 and 1 should correspond to CSI0 and CSI1,
     41  ports 2 and 3 should correspond to DI0 and DI1, respectively.
     42
     43example:
     44
     45ipu: ipu@18000000 {
     46	#address-cells = <1>;
     47	#size-cells = <0>;
     48	compatible = "fsl,imx53-ipu";
     49	reg = <0x18000000 0x080000000>;
     50	interrupts = <11 10>;
     51	resets = <&src 2>;
     52
     53	ipu_di0: port@2 {
     54		reg = <2>;
     55
     56		ipu_di0_disp0: endpoint {
     57			remote-endpoint = <&display_in>;
     58		};
     59	};
     60};
     61
     62Freescale i.MX PRE (Prefetch Resolve Engine)
     63============================================
     64
     65Required properties:
     66- compatible: should be "fsl,imx6qp-pre"
     67- reg: should be register base and length as documented in the
     68  datasheet
     69- clocks : phandle to the PRE axi clock input, as described
     70  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
     71  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
     72- clock-names: should be "axi"
     73- interrupts: should contain the PRE interrupt
     74- fsl,iram: phandle pointing to the mmio-sram device node, that should be
     75  used for the PRE SRAM double buffer.
     76
     77example:
     78
     79pre@21c8000 {
     80	compatible = "fsl,imx6qp-pre";
     81	reg = <0x021c8000 0x1000>;
     82	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
     83	clocks = <&clks IMX6QDL_CLK_PRE0>;
     84	clock-names = "axi";
     85	fsl,iram = <&ocram2>;
     86};
     87
     88Freescale i.MX PRG (Prefetch Resolve Gasket)
     89============================================
     90
     91Required properties:
     92- compatible: should be "fsl,imx6qp-prg"
     93- reg: should be register base and length as documented in the
     94  datasheet
     95- clocks : phandles to the PRG ipg and axi clock inputs, as described
     96  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
     97  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
     98- clock-names: should be "ipg" and "axi"
     99- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
    100  PRE as the first entry and the muxable PREs following.
    101
    102example:
    103
    104prg@21cc000 {
    105	compatible = "fsl,imx6qp-prg";
    106	reg = <0x021cc000 0x1000>;
    107	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
    108		 <&clks IMX6QDL_CLK_PRG0_AXI>;
    109	clock-names = "ipg", "axi";
    110	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
    111};
    112
    113Parallel display support
    114========================
    115
    116Required properties:
    117- compatible: Should be "fsl,imx-parallel-display"
    118Optional properties:
    119- interface-pix-fmt: How this display is connected to the
    120  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
    121  and "lvds666".
    122- edid: verbatim EDID data block describing attached display.
    123- ddc: phandle describing the i2c bus handling the display data
    124  channel
    125- port@[0-1]: Port nodes with endpoint definitions as defined in
    126  Documentation/devicetree/bindings/media/video-interfaces.txt.
    127  Port 0 is the input port connected to the IPU display interface,
    128  port 1 is the output port connected to a panel.
    129
    130example:
    131
    132disp0 {
    133	compatible = "fsl,imx-parallel-display";
    134	edid = [edid-data];
    135	interface-pix-fmt = "rgb24";
    136
    137	port@0 {
    138		reg = <0>;
    139
    140		display_in: endpoint {
    141			remote-endpoint = <&ipu_di0_disp0>;
    142		};
    143	};
    144
    145	port@1 {
    146		reg = <1>;
    147
    148		display_out: endpoint {
    149			remote-endpoint = <&panel_in>;
    150		};
    151	};
    152};
    153
    154panel {
    155	...
    156
    157	port {
    158		panel_in: endpoint {
    159			remote-endpoint = <&display_out>;
    160		};
    161	};
    162};