cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek,rdma.yaml (3750B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Mediatek Read Direct Memory Access
      8
      9maintainers:
     10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
     11  - Philipp Zabel <p.zabel@pengutronix.de>
     12
     13description: |
     14  Mediatek Read Direct Memory Access(RDMA) component used to read the
     15  data into DMA. It provides real time data to the back-end panel
     16  driver, such as DSI, DPI and DP_INTF.
     17  It contains one line buffer to store the sufficient pixel data.
     18  RDMA device node must be siblings to the central MMSYS_CONFIG node.
     19  For a description of the MMSYS_CONFIG binding, see
     20  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
     21  for details.
     22
     23properties:
     24  compatible:
     25    oneOf:
     26      - items:
     27          - const: mediatek,mt2701-disp-rdma
     28      - items:
     29          - const: mediatek,mt8173-disp-rdma
     30      - items:
     31          - const: mediatek,mt8183-disp-rdma
     32      - items:
     33          - const: mediatek,mt8195-disp-rdma
     34      - items:
     35          - enum:
     36              - mediatek,mt7623-disp-rdma
     37              - mediatek,mt2712-disp-rdma
     38          - const: mediatek,mt2701-disp-rdma
     39      - items:
     40          - enum:
     41              - mediatek,mt8186-disp-rdma
     42              - mediatek,mt8192-disp-rdma
     43          - const: mediatek,mt8183-disp-rdma
     44
     45  reg:
     46    maxItems: 1
     47
     48  interrupts:
     49    maxItems: 1
     50
     51  power-domains:
     52    description: A phandle and PM domain specifier as defined by bindings of
     53      the power controller specified by phandle. See
     54      Documentation/devicetree/bindings/power/power-domain.yaml for details.
     55
     56  clocks:
     57    items:
     58      - description: RDMA Clock
     59
     60  iommus:
     61    description:
     62      This property should point to the respective IOMMU block with master port as argument,
     63      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
     64
     65  mediatek,rdma-fifo-size:
     66    description:
     67      rdma fifo size may be different even in same SOC, add this property to the
     68      corresponding rdma.
     69      The value below is the Max value which defined in hardware data sheet
     70      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
     71      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
     72      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
     73    $ref: /schemas/types.yaml#/definitions/uint32
     74    enum: [8192, 5120, 2048]
     75
     76  mediatek,gce-client-reg:
     77    description: The register of client driver can be configured by gce with
     78      4 arguments defined in this property, such as phandle of gce, subsys id,
     79      register offset and size. Each GCE subsys id is mapping to a client
     80      defined in the header include/dt-bindings/gce/<chip>-gce.h.
     81    $ref: /schemas/types.yaml#/definitions/phandle-array
     82    maxItems: 1
     83
     84required:
     85  - compatible
     86  - reg
     87  - interrupts
     88  - power-domains
     89  - clocks
     90  - iommus
     91
     92additionalProperties: false
     93
     94examples:
     95  - |
     96    #include <dt-bindings/interrupt-controller/arm-gic.h>
     97    #include <dt-bindings/clock/mt8173-clk.h>
     98    #include <dt-bindings/power/mt8173-power.h>
     99    #include <dt-bindings/gce/mt8173-gce.h>
    100    #include <dt-bindings/memory/mt8173-larb-port.h>
    101
    102    soc {
    103        #address-cells = <2>;
    104        #size-cells = <2>;
    105
    106        rdma0: rdma@1400e000 {
    107            compatible = "mediatek,mt8173-disp-rdma";
    108            reg = <0 0x1400e000 0 0x1000>;
    109            interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
    110            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    111            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
    112            iommus = <&iommu M4U_PORT_DISP_RDMA0>;
    113            mediatek,rdma-fifo-size = <8192>;
    114            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
    115        };
    116    };