cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dp-controller.yaml (3832B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: MSM Display Port Controller
      8
      9maintainers:
     10  - Kuogee Hsieh <khsieh@codeaurora.org>
     11
     12description: |
     13  Device tree bindings for DisplayPort host controller for MSM targets
     14  that are compatible with VESA DisplayPort interface specification.
     15
     16properties:
     17  compatible:
     18    enum:
     19      - qcom,sc7180-dp
     20      - qcom,sc7280-dp
     21      - qcom,sc7280-edp
     22      - qcom,sc8180x-dp
     23      - qcom,sc8180x-edp
     24      - qcom,sm8350-dp
     25
     26  reg:
     27    items:
     28      - description: ahb register block
     29      - description: aux register block
     30      - description: link register block
     31      - description: p0 register block
     32      - description: p1 register block
     33
     34  interrupts:
     35    maxItems: 1
     36
     37  clocks:
     38    items:
     39      - description: AHB clock to enable register access
     40      - description: Display Port AUX clock
     41      - description: Display Port Link clock
     42      - description: Link interface clock between DP and PHY
     43      - description: Display Port Pixel clock
     44
     45  clock-names:
     46    items:
     47      - const: core_iface
     48      - const: core_aux
     49      - const: ctrl_link
     50      - const: ctrl_link_iface
     51      - const: stream_pixel
     52
     53  assigned-clocks:
     54    items:
     55      - description: link clock source
     56      - description: pixel clock source
     57
     58  assigned-clock-parents:
     59    items:
     60      - description: phy 0 parent
     61      - description: phy 1 parent
     62
     63  phys:
     64    maxItems: 1
     65
     66  phy-names:
     67    items:
     68      - const: dp
     69
     70  operating-points-v2:
     71    maxItems: 1
     72
     73  power-domains:
     74    maxItems: 1
     75
     76  "#sound-dai-cells":
     77    const: 0
     78
     79  ports:
     80    $ref: /schemas/graph.yaml#/properties/ports
     81    properties:
     82      port@0:
     83        $ref: /schemas/graph.yaml#/properties/port
     84        description: Input endpoint of the controller
     85
     86      port@1:
     87        $ref: /schemas/graph.yaml#/properties/port
     88        description: Output endpoint of the controller
     89
     90required:
     91  - compatible
     92  - reg
     93  - interrupts
     94  - clocks
     95  - clock-names
     96  - phys
     97  - phy-names
     98  - "#sound-dai-cells"
     99  - power-domains
    100  - ports
    101
    102additionalProperties: false
    103
    104examples:
    105  - |
    106    #include <dt-bindings/interrupt-controller/arm-gic.h>
    107    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
    108    #include <dt-bindings/power/qcom-rpmpd.h>
    109
    110    displayport-controller@ae90000 {
    111        compatible = "qcom,sc7180-dp";
    112        reg = <0xae90000 0x200>,
    113              <0xae90200 0x200>,
    114              <0xae90400 0xc00>,
    115              <0xae91000 0x400>,
    116              <0xae91400 0x400>;
    117        interrupt-parent = <&mdss>;
    118        interrupts = <12>;
    119        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
    120                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
    121                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
    122                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
    123                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
    124        clock-names = "core_iface", "core_aux",
    125                      "ctrl_link",
    126                      "ctrl_link_iface", "stream_pixel";
    127
    128        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
    129                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
    130
    131        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
    132
    133        phys = <&dp_phy>;
    134        phy-names = "dp";
    135
    136        #sound-dai-cells = <0>;
    137
    138        power-domains = <&rpmhpd SC7180_CX>;
    139
    140        ports {
    141            #address-cells = <1>;
    142            #size-cells = <0>;
    143
    144            port@0 {
    145                reg = <0>;
    146                endpoint {
    147                    remote-endpoint = <&dpu_intf0_out>;
    148                };
    149            };
    150
    151            port@1 {
    152                reg = <1>;
    153                endpoint {
    154                    remote-endpoint = <&typec>;
    155                };
    156            };
    157        };
    158    };
    159...