dpu-sc7280.yaml (6272B)
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DPU dt properties for SC7280 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12description: | 13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15 bindings of MDSS and DPU are mentioned for SC7280. 16 17properties: 18 compatible: 19 const: qcom,sc7280-mdss 20 21 reg: 22 maxItems: 1 23 24 reg-names: 25 const: mdss 26 27 power-domains: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: Display AHB clock from gcc 33 - description: Display AHB clock from dispcc 34 - description: Display core clock 35 36 clock-names: 37 items: 38 - const: iface 39 - const: ahb 40 - const: core 41 42 interrupts: 43 maxItems: 1 44 45 interrupt-controller: true 46 47 "#address-cells": true 48 49 "#size-cells": true 50 51 "#interrupt-cells": 52 const: 1 53 54 iommus: 55 items: 56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 57 58 ranges: true 59 60 interconnects: 61 items: 62 - description: Interconnect path specifying the port ids for data bus 63 64 interconnect-names: 65 const: mdp0-mem 66 67 resets: 68 items: 69 - description: MDSS_CORE reset 70 71patternProperties: 72 "^display-controller@[0-9a-f]+$": 73 type: object 74 description: Node containing the properties of DPU. 75 76 properties: 77 compatible: 78 const: qcom,sc7280-dpu 79 80 reg: 81 items: 82 - description: Address offset and size for mdp register set 83 - description: Address offset and size for vbif register set 84 85 reg-names: 86 items: 87 - const: mdp 88 - const: vbif 89 90 clocks: 91 items: 92 - description: Display hf axi clock 93 - description: Display sf axi clock 94 - description: Display ahb clock 95 - description: Display lut clock 96 - description: Display core clock 97 - description: Display vsync clock 98 99 clock-names: 100 items: 101 - const: bus 102 - const: nrt_bus 103 - const: iface 104 - const: lut 105 - const: core 106 - const: vsync 107 108 interrupts: 109 maxItems: 1 110 111 power-domains: 112 maxItems: 1 113 114 operating-points-v2: true 115 116 ports: 117 $ref: /schemas/graph.yaml#/properties/ports 118 description: | 119 Contains the list of output ports from DPU device. These ports 120 connect to interfaces that are external to the DPU hardware, 121 such as DSI, DP etc. Each output port contains an endpoint that 122 describes how it is connected to an external interface. 123 124 properties: 125 port@0: 126 $ref: /schemas/graph.yaml#/properties/port 127 description: DPU_INTF1 (DSI) 128 129 port@1: 130 $ref: /schemas/graph.yaml#/properties/port 131 description: DPU_INTF5 (EDP) 132 133 required: 134 - port@0 135 136 required: 137 - compatible 138 - reg 139 - reg-names 140 - clocks 141 - interrupts 142 - power-domains 143 - operating-points-v2 144 - ports 145 146required: 147 - compatible 148 - reg 149 - reg-names 150 - power-domains 151 - clocks 152 - interrupts 153 - interrupt-controller 154 - iommus 155 - ranges 156 157additionalProperties: false 158 159examples: 160 - | 161 #include <dt-bindings/clock/qcom,dispcc-sc7280.h> 162 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 163 #include <dt-bindings/interrupt-controller/arm-gic.h> 164 #include <dt-bindings/interconnect/qcom,sc7280.h> 165 #include <dt-bindings/power/qcom-rpmpd.h> 166 167 display-subsystem@ae00000 { 168 #address-cells = <1>; 169 #size-cells = <1>; 170 compatible = "qcom,sc7280-mdss"; 171 reg = <0xae00000 0x1000>; 172 reg-names = "mdss"; 173 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 174 clocks = <&gcc GCC_DISP_AHB_CLK>, 175 <&dispcc DISP_CC_MDSS_AHB_CLK>, 176 <&dispcc DISP_CC_MDSS_MDP_CLK>; 177 clock-names = "iface", 178 "ahb", 179 "core"; 180 181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-controller; 183 #interrupt-cells = <1>; 184 185 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; 186 interconnect-names = "mdp0-mem"; 187 188 iommus = <&apps_smmu 0x900 0x402>; 189 ranges; 190 191 display-controller@ae01000 { 192 compatible = "qcom,sc7280-dpu"; 193 reg = <0x0ae01000 0x8f000>, 194 <0x0aeb0000 0x2008>; 195 196 reg-names = "mdp", "vbif"; 197 198 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 199 <&gcc GCC_DISP_SF_AXI_CLK>, 200 <&dispcc DISP_CC_MDSS_AHB_CLK>, 201 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 202 <&dispcc DISP_CC_MDSS_MDP_CLK>, 203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 204 clock-names = "bus", 205 "nrt_bus", 206 "iface", 207 "lut", 208 "core", 209 "vsync"; 210 211 interrupt-parent = <&mdss>; 212 interrupts = <0>; 213 power-domains = <&rpmhpd SC7280_CX>; 214 operating-points-v2 = <&mdp_opp_table>; 215 216 ports { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 port@0 { 221 reg = <0>; 222 dpu_intf1_out: endpoint { 223 remote-endpoint = <&dsi0_in>; 224 }; 225 }; 226 227 port@1 { 228 reg = <1>; 229 dpu_intf5_out: endpoint { 230 remote-endpoint = <&edp_in>; 231 }; 232 }; 233 }; 234 }; 235 }; 236...