cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dsi-phy-20nm.yaml (1576B)

      1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Display DSI 20nm PHY
      8
      9maintainers:
     10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
     11
     12allOf:
     13  - $ref: dsi-phy-common.yaml#
     14
     15properties:
     16  compatible:
     17    const: qcom,dsi-phy-20nm
     18
     19  reg:
     20    items:
     21      - description: dsi pll register set
     22      - description: dsi phy register set
     23      - description: dsi phy regulator register set
     24
     25  reg-names:
     26    items:
     27      - const: dsi_pll
     28      - const: dsi_phy
     29      - const: dsi_phy_regulator
     30
     31  vcca-supply:
     32    description: Phandle to vcca regulator device node.
     33
     34  vddio-supply:
     35    description: Phandle to vdd-io regulator device node.
     36
     37required:
     38  - compatible
     39  - reg
     40  - reg-names
     41  - vddio-supply
     42  - vcca-supply
     43
     44unevaluatedProperties: false
     45
     46examples:
     47  - |
     48     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     49     #include <dt-bindings/clock/qcom,rpmh.h>
     50
     51     dsi-phy@fd922a00 {
     52         compatible = "qcom,dsi-phy-20nm";
     53         reg = <0xfd922a00 0xd4>,
     54               <0xfd922b00 0x2b0>,
     55               <0xfd922d80 0x7b>;
     56         reg-names = "dsi_pll",
     57                     "dsi_phy",
     58                     "dsi_phy_regulator";
     59
     60         #clock-cells = <1>;
     61         #phy-cells = <0>;
     62
     63         vcca-supply = <&vcca_reg>;
     64         vddio-supply = <&vddio_reg>;
     65
     66         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
     67                  <&rpmhcc RPMH_CXO_CLK>;
     68         clock-names = "iface", "ref";
     69     };
     70...