dsi-phy-7nm.yaml (1625B)
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI 7nm PHY 8 9maintainers: 10 - Jonathan Marek <jonathan@marek.ca> 11 12allOf: 13 - $ref: dsi-phy-common.yaml# 14 15properties: 16 compatible: 17 enum: 18 - qcom,dsi-phy-7nm 19 - qcom,dsi-phy-7nm-8150 20 - qcom,sc7280-dsi-phy-7nm 21 22 reg: 23 items: 24 - description: dsi phy register set 25 - description: dsi phy lane register set 26 - description: dsi pll register set 27 28 reg-names: 29 items: 30 - const: dsi_phy 31 - const: dsi_phy_lane 32 - const: dsi_pll 33 34 vdds-supply: 35 description: | 36 Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) 37 38 phy-type: 39 description: D-PHY (default) or C-PHY mode 40 enum: [ 10, 11 ] 41 default: 10 42 43required: 44 - compatible 45 - reg 46 - reg-names 47 - vdds-supply 48 49unevaluatedProperties: false 50 51examples: 52 - | 53 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 54 #include <dt-bindings/clock/qcom,rpmh.h> 55 56 dsi-phy@ae94400 { 57 compatible = "qcom,dsi-phy-7nm"; 58 reg = <0x0ae94400 0x200>, 59 <0x0ae94600 0x280>, 60 <0x0ae94900 0x260>; 61 reg-names = "dsi_phy", 62 "dsi_phy_lane", 63 "dsi_pll"; 64 65 #clock-cells = <1>; 66 #phy-cells = <0>; 67 68 vdds-supply = <&vreg_l5a_0p88>; 69 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 70 <&rpmhcc RPMH_CXO_CLK>; 71 clock-names = "iface", "ref"; 72 };