cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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panel-mipi-dbi-spi.yaml (3798B)

      1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: MIPI DBI SPI Panel
      8
      9maintainers:
     10  - Noralf Trønnes <noralf@tronnes.org>
     11
     12description: |
     13  This binding is for display panels using a MIPI DBI compatible controller
     14  in SPI mode.
     15
     16  The MIPI Alliance Standard for Display Bus Interface defines the electrical
     17  and logical interfaces for display controllers historically used in mobile
     18  phones. The standard defines 4 display architecture types and this binding is
     19  for type 1 which has full frame memory. There are 3 interface types in the
     20  standard and type C is the serial interface.
     21
     22  The standard defines the following interface signals for type C:
     23  - Power:
     24    - Vdd: Power supply for display module
     25    - Vddi: Logic level supply for interface signals
     26    Combined into one in this binding called: power-supply
     27  - Interface:
     28    - CSx: Chip select
     29    - SCL: Serial clock
     30    - Dout: Serial out
     31    - Din: Serial in
     32    - SDA: Bidrectional in/out
     33    - D/CX: Data/command selection, high=data, low=command
     34      Called dc-gpios in this binding.
     35    - RESX: Reset when low
     36      Called reset-gpios in this binding.
     37
     38  The type C interface has 3 options:
     39
     40    - Option 1: 9-bit mode and D/CX as the 9th bit
     41      |              Command              |  the next command or following data  |
     42      |<0><D7><D6><D5><D4><D3><D2><D1><D0>|<D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
     43
     44    - Option 2: 16-bit mode and D/CX as a 9th bit
     45      |              Command or data                              |
     46      |<X><X><X><X><X><X><X><D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
     47
     48    - Option 3: 8-bit mode and D/CX as a separate interface line
     49      |        Command or data         |
     50      |<D7><D6><D5><D4><D3><D2><D1><D0>|
     51
     52  The panel resolution is specified using the panel-timing node properties
     53  hactive (width) and vactive (height). The other mandatory panel-timing
     54  properties should be set to zero except clock-frequency which can be
     55  optionally set to inform about the actual pixel clock frequency.
     56
     57  If the panel is wired to the controller at an offset specify this using
     58  hback-porch (x-offset) and vback-porch (y-offset).
     59
     60allOf:
     61  - $ref: panel-common.yaml#
     62  - $ref: /schemas/spi/spi-peripheral-props.yaml#
     63
     64properties:
     65  compatible:
     66    items:
     67      - enum:
     68          - sainsmart18
     69      - const: panel-mipi-dbi-spi
     70
     71  write-only:
     72    type: boolean
     73    description:
     74      Controller is not readable (ie. Din (MISO on the SPI interface) is not
     75      wired up).
     76
     77  dc-gpios:
     78    maxItems: 1
     79    description: |
     80      Controller data/command selection (D/CX) in 4-line SPI mode.
     81      If not set, the controller is in 3-line SPI mode.
     82
     83required:
     84  - compatible
     85  - reg
     86  - width-mm
     87  - height-mm
     88  - panel-timing
     89
     90unevaluatedProperties: false
     91
     92examples:
     93  - |
     94    #include <dt-bindings/gpio/gpio.h>
     95
     96    spi {
     97        #address-cells = <1>;
     98        #size-cells = <0>;
     99
    100        display@0{
    101            compatible = "sainsmart18", "panel-mipi-dbi-spi";
    102            reg = <0>;
    103            spi-max-frequency = <40000000>;
    104
    105            dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
    106            reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
    107            write-only;
    108
    109            backlight = <&backlight>;
    110
    111            width-mm = <35>;
    112            height-mm = <28>;
    113
    114            panel-timing {
    115                hactive = <160>;
    116                vactive = <128>;
    117                hback-porch = <0>;
    118                vback-porch = <0>;
    119                clock-frequency = <0>;
    120                hfront-porch = <0>;
    121                hsync-len = <0>;
    122                vfront-porch = <0>;
    123                vsync-len = <0>;
    124            };
    125        };
    126    };
    127
    128...