cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sprd,sharkl3-dsi-host.yaml (1833B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Unisoc MIPI DSI Controller
      8
      9maintainers:
     10  - Kevin Tang <kevin.tang@unisoc.com>
     11
     12properties:
     13  compatible:
     14    const: sprd,sharkl3-dsi-host
     15
     16  reg:
     17    maxItems: 1
     18
     19  interrupts:
     20    maxItems: 2
     21
     22  clocks:
     23    minItems: 1
     24
     25  clock-names:
     26    items:
     27      - const: clk_src_96m
     28
     29  power-domains:
     30    maxItems: 1
     31
     32  ports:
     33    type: object
     34
     35    properties:
     36      "#address-cells":
     37        const: 1
     38
     39      "#size-cells":
     40        const: 0
     41
     42      port@0:
     43        type: object
     44        description:
     45          A port node with endpoint definitions as defined in
     46          Documentation/devicetree/bindings/media/video-interfaces.txt.
     47          That port should be the input endpoint, usually coming from
     48          the associated DPU.
     49
     50    required:
     51      - "#address-cells"
     52      - "#size-cells"
     53      - port@0
     54
     55    additionalProperties: false
     56
     57required:
     58  - compatible
     59  - reg
     60  - interrupts
     61  - clocks
     62  - clock-names
     63  - ports
     64
     65additionalProperties: false
     66
     67examples:
     68  - |
     69    #include <dt-bindings/interrupt-controller/arm-gic.h>
     70    #include <dt-bindings/clock/sprd,sc9860-clk.h>
     71    dsi: dsi@63100000 {
     72        compatible = "sprd,sharkl3-dsi-host";
     73        reg = <0x63100000 0x1000>;
     74        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
     75          <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
     76        clock-names = "clk_src_96m";
     77        clocks = <&pll CLK_TWPLL_96M>;
     78        ports {
     79            #address-cells = <1>;
     80            #size-cells = <0>;
     81            port@0 {
     82                reg = <0>;
     83                dsi_in: endpoint {
     84                    remote-endpoint = <&dpu_out>;
     85                };
     86            };
     87        };
     88    };