cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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moxa,moxart-dma.txt (1094B)


      1MOXA ART DMA Controller
      2
      3See dma.txt first
      4
      5Required properties:
      6
      7- compatible :	Must be "moxa,moxart-dma"
      8- reg :		Should contain registers location and length
      9- interrupts :	Should contain an interrupt-specifier for the sole
     10		interrupt generated by the device
     11- #dma-cells :	Should be 1, a single cell holding a line request number
     12
     13Example:
     14
     15	dma: dma@90500000 {
     16		compatible = "moxa,moxart-dma";
     17		reg = <0x90500080 0x40>;
     18		interrupts = <24 0>;
     19		#dma-cells = <1>;
     20	};
     21
     22
     23Clients:
     24
     25DMA clients connected to the MOXA ART DMA controller must use the format
     26described in the dma.txt file, using a two-cell specifier for each channel:
     27a phandle plus one integer cells.
     28The two cells in order are:
     29
     301. A phandle pointing to the DMA controller.
     312. Peripheral identifier for the hardware handshaking interface.
     32
     33Example:
     34Use specific request line passing from dma
     35For example, MMC request line is 5
     36
     37	sdhci: sdhci@98e00000 {
     38		compatible = "moxa,moxart-sdhci";
     39		reg = <0x98e00000 0x5C>;
     40		interrupts = <5 0>;
     41		clocks = <&clk_apb>;
     42		dmas =  <&dma 5>,
     43			<&dma 5>;
     44		dma-names = "tx", "rx";
     45	};