cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mv-xor-v2.txt (765B)


      1* Marvell XOR v2 engines
      2
      3Required properties:
      4- compatible: one of the following values:
      5    "marvell,armada-7k-xor"
      6    "marvell,xor-v2"
      7- reg: Should contain registers location and length (two sets)
      8    the first set is the DMA registers
      9    the second set is the global registers
     10- msi-parent: Phandle to the MSI-capable interrupt controller used for
     11  interrupts.
     12
     13Optional properties:
     14- clocks: Optional reference to the clocks used by the XOR engine.
     15- clock-names: mandatory if there is a second clock, in this case the
     16   name must be "core" for the first clock and "reg" for the second
     17   one
     18
     19
     20Example:
     21
     22	xor0@400000 {
     23		compatible = "marvell,xor-v2";
     24		reg = <0x400000 0x1000>,
     25		      <0x410000 0x1000>;
     26		msi-parent = <&gic_v2m0>;
     27		dma-coherent;
     28	};