cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mv-xor.txt (1213B)

      1* Marvell XOR engines
      2
      3Required properties:
      4- compatible: Should be one of the following:
      5  - "marvell,orion-xor"
      6  - "marvell,armada-380-xor"
      7  - "marvell,armada-3700-xor".
      8- reg: Should contain registers location and length (two sets)
      9    the first set is the low registers, the second set the high
     10    registers for the XOR engine.
     11- clocks: pointer to the reference clock
     12
     13The DT node must also contains sub-nodes for each XOR channel that the
     14XOR engine has. Those sub-nodes have the following required
     15properties:
     16- interrupts: interrupt of the XOR channel
     17
     18The sub-nodes used to contain one or several of the following
     19properties, but they are now deprecated:
     20- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
     21- dmacap,memset to indicate that the XOR channel is capable of memset operations
     22- dmacap,xor to indicate that the XOR channel is capable of xor operations
     23- dmacap,interrupt to indicate that the XOR channel is capable of
     24  generating interrupts
     25
     26Example:
     27
     28xor@d0060900 {
     29	compatible = "marvell,orion-xor";
     30	reg = <0xd0060900 0x100
     31	       0xd0060b00 0x100>;
     32	clocks = <&coreclk 0>;
     33
     34	xor00 {
     35	      interrupts = <51>;
     36	};
     37	xor01 {
     38	      interrupts = <52>;
     39	};
     40};