cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom_bam_dma.txt (1765B)


      1QCOM BAM DMA controller
      2
      3Required properties:
      4- compatible: must be one of the following:
      5 * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
      6 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
      7 * "qcom,bam-v1.7.0" for MSM8916
      8- reg: Address range for DMA registers
      9- interrupts: Should contain the one interrupt shared by all channels
     10- #dma-cells: must be <1>, the cell in the dmas property of the client device
     11  represents the channel number
     12- clocks: required clock
     13- clock-names: must contain "bam_clk" entry
     14- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
     15  the secure world.
     16- qcom,controlled-remotely : optional, indicates that the bam is controlled by
     17  remote proccessor i.e. execution environment.
     18- qcom,powered-remotely : optional, indicates that the bam is powered up by
     19  a remote processor but must be initialized by the local processor.
     20- num-channels : optional, indicates supported number of DMA channels in a
     21  remotely controlled bam.
     22- qcom,num-ees : optional, indicates supported number of Execution Environments
     23  in a remotely controlled bam.
     24
     25Example:
     26
     27	uart-bam: dma@f9984000 = {
     28		compatible = "qcom,bam-v1.4.0";
     29		reg = <0xf9984000 0x15000>;
     30		interrupts = <0 94 0>;
     31		clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
     32		clock-names = "bam_clk";
     33		#dma-cells = <1>;
     34		qcom,ee = <0>;
     35	};
     36
     37DMA clients must use the format described in the dma.txt file, using a two cell
     38specifier for each channel.
     39
     40Example:
     41	serial@f991e000 {
     42		compatible = "qcom,msm-uart";
     43		reg = <0xf991e000 0x1000>
     44			<0xf9944000 0x19000>;
     45		interrupts = <0 108 0>;
     46		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
     47			<&gcc GCC_BLSP1_AHB_CLK>;
     48		clock-names = "core", "iface";
     49
     50		dmas = <&uart-bam 0>, <&uart-bam 1>;
     51		dma-names = "rx", "tx";
     52	};