xilinx_dma.txt (4657B)
1Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2It can be configured to have one channel or two channels. If configured 3as two channels, one is to transmit to the video device and another is 4to receive from the video device. 5 6Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7target devices. It can be configured to have one channel or two channels. 8If configured as two channels, one is to transmit to the device and another 9is to receive from the device. 10 11Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12address and a memory-mapped destination address. 13 14Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 15target devices. It can be configured to have up to 16 independent transmit 16and receive channels. 17 18Required properties: 19- compatible: Should be one of- 20 "xlnx,axi-vdma-1.00.a" 21 "xlnx,axi-dma-1.00.a" 22 "xlnx,axi-cdma-1.00.a" 23 "xlnx,axi-mcdma-1.00.a" 24- #dma-cells: Should be <1>, see "dmas" property below 25- reg: Should contain VDMA registers location and length. 26- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 27- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 28- dma-channel child node: Should have at least one channel and can have up to 29 two channels per device. This node specifies the properties of each 30 DMA channel (see child node properties below). 31- clocks: Input clock specifier. Refer to common clock bindings. 32- clock-names: List of input clocks 33 For VDMA: 34 Required elements: "s_axi_lite_aclk" 35 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 36 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 37 For CDMA: 38 Required elements: "s_axi_lite_aclk", "m_axi_aclk" 39 For AXIDMA and MCDMA: 40 Required elements: "s_axi_lite_aclk" 41 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 42 "m_axi_sg_aclk" 43 44Required properties for VDMA: 45- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 46 47Optional properties for AXI DMA and MCDMA: 48- xlnx,sg-length-width: Should be set to the width in bits of the length 49 register as configured in h/w. Takes values {8...26}. If the property 50 is missing or invalid then the default value 23 is used. This is the 51 maximum value that is supported by all IP versions. 52Optional properties for VDMA: 53- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 54 It takes following values: 55 {1}, flush both channels 56 {2}, flush mm2s channel 57 {3}, flush s2mm channel 58 59Required child node properties: 60- compatible: 61 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 62 "xlnx,axi-vdma-s2mm-channel". 63 For CDMA: It should be "xlnx,axi-cdma-channel". 64 For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" 65 or "xlnx,axi-dma-s2mm-channel". 66- interrupts: Should contain per channel VDMA interrupts. 67- xlnx,datawidth: Should contain the stream data width, take values 68 {32,64...1024}. 69 70Optional child node properties: 71- xlnx,include-dre: Tells hardware is configured for Data 72 Realignment Engine. 73Optional child node properties for VDMA: 74- xlnx,genlock-mode: Tells Genlock synchronization is 75 enabled/disabled in hardware. 76- xlnx,enable-vert-flip: Tells vertical flip is 77 enabled/disabled in hardware(S2MM path). 78Optional child node properties for MCDMA: 79- dma-channels: Number of dma channels in child node. 80 81Example: 82++++++++ 83 84axi_vdma_0: axivdma@40030000 { 85 compatible = "xlnx,axi-vdma-1.00.a"; 86 #dma_cells = <1>; 87 reg = < 0x40030000 0x10000 >; 88 dma-ranges = <0x00000000 0x00000000 0x40000000>; 89 xlnx,num-fstores = <0x8>; 90 xlnx,flush-fsync = <0x1>; 91 xlnx,addrwidth = <0x20>; 92 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 93 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 94 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 95 dma-channel@40030000 { 96 compatible = "xlnx,axi-vdma-mm2s-channel"; 97 interrupts = < 0 54 4 >; 98 xlnx,datawidth = <0x40>; 99 } ; 100 dma-channel@40030030 { 101 compatible = "xlnx,axi-vdma-s2mm-channel"; 102 interrupts = < 0 53 4 >; 103 xlnx,datawidth = <0x40>; 104 } ; 105} ; 106 107 108* DMA client 109 110Required properties: 111- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, 112 where Channel ID is '0' for write/tx and '1' for read/rx 113 channel. For MCMDA, MM2S channel(write/tx) ID start from 114 '0' and is in [0-15] range. S2MM channel(read/rx) ID start 115 from '16' and is in [16-31] range. These channels ID are 116 fixed irrespective of IP configuration. 117 118- dma-names: a list of DMA channel names, one per "dmas" entry 119 120Example: 121++++++++ 122 123vdmatest_0: vdmatest@0 { 124 compatible ="xlnx,axi-vdma-test-1.00.a"; 125 dmas = <&axi_vdma_0 0 126 &axi_vdma_0 1>; 127 dma-names = "vdma0", "vdma1"; 128} ;