cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xlnx,zynqmp-dma-1.0.yaml (1781B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Xilinx ZynqMP DMA Engine
      8
      9description: |
     10  The Xilinx ZynqMP DMA engine supports memory to memory transfers,
     11  memory to device and device to memory transfers. It also has flow
     12  control and rate control support for slave/peripheral dma access.
     13
     14maintainers:
     15  - Michael Tretter <m.tretter@pengutronix.de>
     16
     17allOf:
     18  - $ref: "../dma-controller.yaml#"
     19
     20properties:
     21  "#dma-cells":
     22    const: 1
     23
     24  compatible:
     25    const: xlnx,zynqmp-dma-1.0
     26
     27  reg:
     28    description: memory map for gdma/adma module access
     29    maxItems: 1
     30
     31  interrupts:
     32    description: DMA channel interrupt
     33    maxItems: 1
     34
     35  clocks:
     36    description: input clocks
     37    minItems: 2
     38    maxItems: 2
     39
     40  clock-names:
     41    items:
     42      - const: clk_main
     43      - const: clk_apb
     44
     45  xlnx,bus-width:
     46    $ref: /schemas/types.yaml#/definitions/uint32
     47    enum:
     48      - 64
     49      - 128
     50    description: AXI bus width in bits
     51
     52  iommus:
     53    maxItems: 1
     54
     55  power-domains:
     56    maxItems: 1
     57
     58  dma-coherent:
     59    description: present if dma operations are coherent
     60
     61required:
     62  - "#dma-cells"
     63  - compatible
     64  - reg
     65  - interrupts
     66  - clocks
     67  - clock-names
     68
     69additionalProperties: false
     70
     71examples:
     72  - |
     73    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
     74
     75    fpd_dma_chan1: dma-controller@fd500000 {
     76      compatible = "xlnx,zynqmp-dma-1.0";
     77      reg = <0xfd500000 0x1000>;
     78      interrupt-parent = <&gic>;
     79      interrupts = <0 117 0x4>;
     80      #dma-cells = <1>;
     81      clock-names = "clk_main", "clk_apb";
     82      clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
     83      xlnx,bus-width = <128>;
     84      dma-coherent;
     85    };