cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xlnx,zynqmp-dpdma.yaml (1499B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
      8
      9description: |
     10  These bindings describe the DMA engine included in the Xilinx ZynqMP
     11  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
     12  channels for a video stream, 1 channel for a graphics stream, and 2 channels
     13  for an audio stream).
     14
     15maintainers:
     16  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
     17
     18allOf:
     19  - $ref: "../dma-controller.yaml#"
     20
     21properties:
     22  "#dma-cells":
     23    const: 1
     24    description: |
     25      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
     26      for a list of channel IDs).
     27
     28  compatible:
     29    const: xlnx,zynqmp-dpdma
     30
     31  reg:
     32    maxItems: 1
     33
     34  interrupts:
     35    maxItems: 1
     36
     37  clocks:
     38    description: The AXI clock
     39    maxItems: 1
     40
     41  clock-names:
     42    const: axi_clk
     43
     44required:
     45  - "#dma-cells"
     46  - compatible
     47  - reg
     48  - interrupts
     49  - clocks
     50  - clock-names
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/interrupt-controller/arm-gic.h>
     57
     58    dma: dma-controller@fd4c0000 {
     59      compatible = "xlnx,zynqmp-dpdma";
     60      reg = <0xfd4c0000 0x1000>;
     61      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
     62      interrupt-parent = <&gic>;
     63      clocks = <&dpdma_clk>;
     64      clock-names = "axi_clk";
     65      #dma-cells = <1>;
     66    };
     67
     68...