cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qemu,fw-cfg-mmio.yaml (1415B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: QEMU Firmware Configuration bindings
      8
      9maintainers:
     10  - Rob Herring <robh@kernel.org>
     11
     12description: |
     13  Various QEMU emulation / virtualization targets provide the following
     14  Firmware Configuration interface on the "virt" machine type:
     15
     16  - A write-only, 16-bit wide selector (or control) register,
     17  - a read-write, 64-bit wide data register.
     18
     19  QEMU exposes the control and data register to guests as memory mapped
     20  registers; their location is communicated to the guest's UEFI firmware in the
     21  DTB that QEMU places at the bottom of the guest's DRAM.
     22
     23  The authoritative guest-side hardware interface documentation to the fw_cfg
     24  device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
     25
     26
     27properties:
     28  compatible:
     29    const: qemu,fw-cfg-mmio
     30
     31  reg:
     32    maxItems: 1
     33    description: |
     34      * Bytes 0x0 to 0x7 cover the data register.
     35      * Bytes 0x8 to 0x9 cover the selector register.
     36      * Further registers may be appended to the region in case of future interface
     37        revisions / feature bits.
     38
     39  dma-coherent: true
     40
     41required:
     42  - compatible
     43  - reg
     44
     45additionalProperties: false
     46
     47examples:
     48  - |
     49
     50    fw-cfg@9020000 {
     51        compatible = "qemu,fw-cfg-mmio";
     52        reg = <0x9020000 0xa>;
     53    };
     54...