cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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altera-hps2fpga-bridge.txt (1044B)

      1Altera FPGA/HPS Bridge Driver
      2
      3Required properties:
      4- regs		: base address and size for AXI bridge module
      5- compatible	: Should contain one of:
      6		  "altr,socfpga-lwhps2fpga-bridge",
      7		  "altr,socfpga-hps2fpga-bridge", or
      8		  "altr,socfpga-fpga2hps-bridge"
      9- resets	: Phandle and reset specifier for this bridge's reset
     10- clocks	: Clocks used by this module.
     11
     12See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
     13
     14Example:
     15	fpga_bridge0: fpga-bridge@ff400000 {
     16		compatible = "altr,socfpga-lwhps2fpga-bridge";
     17		reg = <0xff400000 0x100000>;
     18		resets = <&rst LWHPS2FPGA_RESET>;
     19		clocks = <&l4_main_clk>;
     20		bridge-enable = <0>;
     21	};
     22
     23	fpga_bridge1: fpga-bridge@ff500000 {
     24		compatible = "altr,socfpga-hps2fpga-bridge";
     25		reg = <0xff500000 0x10000>;
     26		resets = <&rst HPS2FPGA_RESET>;
     27		clocks = <&l4_main_clk>;
     28		bridge-enable = <1>;
     29	};
     30
     31	fpga_bridge2: fpga-bridge@ff600000 {
     32		compatible = "altr,socfpga-fpga2hps-bridge";
     33		reg = <0xff600000 0x100000>;
     34		resets = <&rst FPGA2HPS_RESET>;
     35		clocks = <&l4_main_clk>;
     36	};