cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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8xxx_gpio.txt (2400B)

      1GPIO controllers on MPC8xxx SoCs
      2
      3This is for the non-QE/CPM/GUTs GPIO controllers as found on
      48349, 8572, 8610 and compatible.
      5
      6Every GPIO controller node must have #gpio-cells property defined,
      7this information will be used to translate gpio-specifiers.
      8See bindings/gpio/gpio.txt for details of how to specify GPIO
      9information for devices.
     10
     11The GPIO module usually is connected to the SoC's internal interrupt
     12controller, see bindings/interrupt-controller/interrupts.txt (the
     13interrupt client nodes section) for details how to specify this GPIO
     14module's interrupt.
     15
     16The GPIO module may serve as another interrupt controller (cascaded to
     17the SoC's internal interrupt controller).  See the interrupt controller
     18nodes section in bindings/interrupt-controller/interrupts.txt for
     19details.
     20
     21Required properties:
     22- compatible:		"fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
     23			for 83xx, "fsl,mpc8572-gpio" for 85xx, or
     24			"fsl,mpc8610-gpio" for 86xx.
     25- #gpio-cells:		Should be two. The first cell is the pin number
     26			and the second cell is used to specify optional
     27			parameters (currently unused).
     28- interrupts:		Interrupt mapping for GPIO IRQ.
     29- gpio-controller:	Marks the port as GPIO controller.
     30
     31Optional properties:
     32- interrupt-controller:	Empty boolean property which marks the GPIO
     33			module as an IRQ controller.
     34- #interrupt-cells:	Should be two.  Defines the number of integer
     35			cells required to specify an interrupt within
     36			this interrupt controller.  The first cell
     37			defines the pin number, the second cell
     38			defines additional flags (trigger type,
     39			trigger polarity).  Note that the available
     40			set of trigger conditions supported by the
     41			GPIO module depends on the actual SoC.
     42
     43Example of gpio-controller nodes for a MPC8347 SoC:
     44
     45	gpio1: gpio-controller@c00 {
     46		#gpio-cells = <2>;
     47		compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
     48		reg = <0xc00 0x100>;
     49		interrupt-parent = <&ipic>;
     50		interrupts = <74 0x8>;
     51		gpio-controller;
     52		interrupt-controller;
     53		#interrupt-cells = <2>;
     54	};
     55
     56	gpio2: gpio-controller@d00 {
     57		#gpio-cells = <2>;
     58		compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
     59		reg = <0xd00 0x100>;
     60		interrupt-parent = <&ipic>;
     61		interrupts = <75 0x8>;
     62		gpio-controller;
     63	};
     64
     65Example of a peripheral using the GPIO module as an IRQ controller:
     66
     67	funkyfpga@0 {
     68		compatible = "funky-fpga";
     69		...
     70		interrupt-parent = <&gpio1>;
     71		interrupts = <4 3>;
     72	};