cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

brcm,xgs-iproc-gpio.yaml (1485B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc-gpio.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Broadcom XGS iProc GPIO controller
      8
      9maintainers:
     10  - Chris Packham <chris.packham@alliedtelesis.co.nz>
     11
     12description: |
     13  This controller is the Chip Common A GPIO present on a number of Broadcom
     14  switch ASICs with integrated SoCs.
     15
     16properties:
     17  compatible:
     18    const: brcm,iproc-gpio-cca
     19
     20  reg:
     21    items:
     22      - description: the I/O address containing the GPIO controller registers.
     23      - description: the I/O address containing the Chip Common A interrupt registers.
     24
     25  gpio-controller: true
     26
     27  '#gpio-cells':
     28    const: 2
     29
     30  ngpios:
     31    minimum: 0
     32    maximum: 32
     33
     34  interrupt-controller: true
     35
     36  '#interrupt-cells':
     37    const: 2
     38
     39  interrupts:
     40    maxItems: 1
     41
     42required:
     43  - compatible
     44  - reg
     45  - "#gpio-cells"
     46  - gpio-controller
     47
     48additionalProperties: false
     49
     50dependencies:
     51  interrupt-controller: [ interrupts ]
     52
     53examples:
     54  - |
     55    #include <dt-bindings/interrupt-controller/irq.h>
     56    #include <dt-bindings/interrupt-controller/arm-gic.h>
     57    gpio@18000060 {
     58        compatible = "brcm,iproc-gpio-cca";
     59        #gpio-cells = <2>;
     60        reg = <0x18000060 0x50>,
     61              <0x18000000 0x50>;
     62        ngpios = <12>;
     63        gpio-controller;
     64        interrupt-controller;
     65        #interrupt-cells = <2>;
     66        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
     67    };
     68
     69
     70...