cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cdns,gpio.txt (1377B)


      1Cadence GPIO controller bindings
      2
      3Required properties:
      4- compatible: should be "cdns,gpio-r1p02".
      5- reg: the register base address and size.
      6- #gpio-cells: should be 2.
      7	* first cell is the GPIO number.
      8	* second cell specifies the GPIO flags, as defined in
      9		<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
     10		and GPIO_ACTIVE_LOW flags are supported.
     11- gpio-controller: marks the device as a GPIO controller.
     12- clocks: should contain one entry referencing the peripheral clock driving
     13	the GPIO controller.
     14
     15Optional properties:
     16- ngpios: integer number of gpio lines supported by this controller, up to 32.
     17- interrupts: interrupt specifier for the controllers interrupt.
     18- interrupt-controller: marks the device as an interrupt controller. When
     19	defined, interrupts, interrupt-parent and #interrupt-cells
     20	are required.
     21- interrupt-cells: should be 2.
     22	* first cell is the GPIO number you want to use as an IRQ source.
     23	* second cell specifies the IRQ type, as defined in
     24		<dt-bindings/interrupt-controller/irq.h>.
     25		Currently only level sensitive IRQs are supported.
     26
     27
     28Example:
     29	gpio0: gpio-controller@fd060000 {
     30		compatible = "cdns,gpio-r1p02";
     31		reg =<0xfd060000 0x1000>;
     32
     33		clocks = <&gpio_clk>;
     34
     35		interrupt-parent = <&gic>;
     36		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
     37
     38		gpio-controller;
     39		#gpio-cells = <2>;
     40
     41		interrupt-controller;
     42		#interrupt-cells = <2>;
     43	};