cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fairchild,74hc595.yaml (1577B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Generic 8-bit shift register
      8
      9maintainers:
     10  - Maxime Ripard <mripard@kernel.org>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - fairchild,74hc595
     16      - nxp,74lvc594
     17
     18  reg:
     19    maxItems: 1
     20
     21  gpio-controller: true
     22
     23  '#gpio-cells':
     24    description:
     25      The second cell is only used to specify the GPIO polarity.
     26    const: 2
     27
     28  registers-number:
     29    $ref: /schemas/types.yaml#/definitions/uint32
     30    description: Number of daisy-chained shift registers
     31
     32  enable-gpios:
     33    description: GPIO connected to the OE (Output Enable) pin.
     34    maxItems: 1
     35
     36  spi-max-frequency: true
     37
     38patternProperties:
     39  "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
     40    type: object
     41
     42    properties:
     43      gpio-hog: true
     44      gpios: true
     45      output-high: true
     46      output-low: true
     47      line-name: true
     48
     49    required:
     50      - gpio-hog
     51      - gpios
     52
     53    additionalProperties: false
     54
     55required:
     56  - compatible
     57  - reg
     58  - gpio-controller
     59  - '#gpio-cells'
     60  - registers-number
     61
     62additionalProperties: false
     63
     64examples:
     65  - |
     66    spi {
     67            #address-cells = <1>;
     68            #size-cells = <0>;
     69
     70            gpio5: gpio5@0 {
     71                    compatible = "fairchild,74hc595";
     72                    reg = <0>;
     73                    gpio-controller;
     74                    #gpio-cells = <2>;
     75                    registers-number = <4>;
     76                    spi-max-frequency = <100000>;
     77            };
     78    };