cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpio-stp-xway.yaml (2517B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Lantiq SoC Serial To Parallel (STP) GPIO controller
      8
      9description: |
     10  The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
     11  peripheral controller used to drive external shift register cascades. At most
     12  3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
     13  and Ethernet PHYs to drive some bytes of the cascade automatically.
     14
     15maintainers:
     16  - John Crispin <john@phrozen.org>
     17
     18properties:
     19  $nodename:
     20    pattern: "^gpio@[0-9a-f]+$"
     21
     22  compatible:
     23    const: lantiq,gpio-stp-xway
     24
     25  reg:
     26    maxItems: 1
     27
     28  gpio-controller: true
     29
     30  "#gpio-cells":
     31    description:
     32      The first cell is the pin number and the second cell is used to specify
     33      consumer flags.
     34    const: 2
     35
     36  lantiq,shadow:
     37    description:
     38      The default value that we shall assume as already set on the
     39      shift register cascade.
     40    $ref: /schemas/types.yaml#/definitions/uint32
     41    minimum: 0x000000
     42    maximum: 0xffffff
     43
     44  lantiq,groups:
     45    description:
     46      Set the 3 bit mask to select which of the 3 groups are enabled
     47      in the shift register cascade.
     48    $ref: /schemas/types.yaml#/definitions/uint32
     49    minimum: 0x0
     50    maximum: 0x7
     51
     52  lantiq,dsl:
     53    description:
     54      The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
     55      property can enable this feature.
     56    $ref: /schemas/types.yaml#/definitions/uint32
     57    minimum: 0x0
     58    maximum: 0x3
     59
     60  lantiq,rising:
     61    description:
     62      Use rising instead of falling edge for the shift register.
     63    type: boolean
     64
     65patternProperties:
     66  "^lantiq,phy[1-4]$":
     67    description:
     68      The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
     69      phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
     70    $ref: /schemas/types.yaml#/definitions/uint32
     71    minimum: 0x0
     72    maximum: 0x7
     73
     74required:
     75  - compatible
     76  - reg
     77  - gpio-controller
     78  - "#gpio-cells"
     79
     80additionalProperties: false
     81
     82examples:
     83  - |
     84    gpio@e100bb0 {
     85        compatible = "lantiq,gpio-stp-xway";
     86        reg = <0xE100BB0 0x40>;
     87        #gpio-cells = <2>;
     88        gpio-controller;
     89
     90        pinctrl-0 = <&stp_pins>;
     91        pinctrl-names = "default";
     92
     93        lantiq,shadow = <0xffffff>;
     94        lantiq,groups = <0x7>;
     95        lantiq,dsl = <0x3>;
     96        lantiq,phy1 = <0x7>;
     97        lantiq,phy2 = <0x7>;
     98    };
     99...