cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpio_oxnas.txt (1432B)

      1* Oxford Semiconductor OXNAS SoC GPIO Controller
      2
      3Please refer to gpio.txt for generic information regarding GPIO bindings.
      4
      5Required properties:
      6 - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
      7 - reg: Base address and length for the device.
      8 - interrupts: The port interrupt shared by all pins.
      9 - gpio-controller: Marks the port as GPIO controller.
     10 - #gpio-cells: Two. The first cell is the pin number and
     11   the second cell is used to specify the gpio polarity as defined in
     12   defined in <dt-bindings/gpio/gpio.h>:
     13      0 = GPIO_ACTIVE_HIGH
     14      1 = GPIO_ACTIVE_LOW
     15 - interrupt-controller: Marks the device node as an interrupt controller.
     16 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
     17   is used to specify the trigger type as defined in
     18   <dt-bindings/interrupt-controller/irq.h>:
     19      IRQ_TYPE_EDGE_RISING
     20      IRQ_TYPE_EDGE_FALLING
     21      IRQ_TYPE_EDGE_BOTH
     22 - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
     23   gpio base and count, should be in the format of numeric-gpio-range as
     24   specified in the gpio.txt file.
     25
     26Example:
     27
     28gpio0: gpio@0 {
     29	compatible = "oxsemi,ox810se-gpio";
     30	reg = <0x000000 0x100000>;
     31	interrupts = <21>;
     32	#gpio-cells = <2>;
     33	gpio-controller;
     34	interrupt-controller;
     35	#interrupt-cells = <2>;
     36	gpio-ranges = <&pinctrl 0 0 32>;
     37};
     38
     39keys {
     40	...
     41
     42	button-esc {
     43		label = "ESC";
     44		linux,code = <1>;
     45		gpios = <&gpio0 12 0>;
     46	};
     47};